AD1895 datasheet(3/24 Pages) AD

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REV. B

–3–

AD1895

DIGITAL TIMING (–40 C < TA < +105 C, VDD_CORE = 3.3 V

5%, VDD_IO = 5.0 V

10%)

Parameter

Min

Max

Unit

tMCLKI

MCLK_IN Period

33.3

fMCLK

MCLK_IN Frequency

30.0

2, 3

MHz

tMPWH

MCLK_IN Pulsewidth High

tMPWL

MCLK_IN Pulsewidth Low

INPUT SERIAL PORT TIMING

tLRIS

LRCLK_I Setup to SCLK_I

tSIH

SCLK_I Pulsewidth High

tSIL

SCLK_I Pulsewidth Low

tDIS

SDATA_I Setup to SCLK_I Rising Edge

tDIH

SDATA_I Hold from SCLK_I Rising Edge

OUTPUT SERIAL PORT TIMING

tTDMS

TDM_IN Setup to SCLK_O Falling Edge

tTDMH

TDM_IN Hold from SCLK_O Falling Edge

tDOPD

SDATA_O Propagation Delay from SCLK_O, LRCLK_O

tDOH

SDATA_O Hold from SCLK_O

tLROS

LRCLK_O Setup to SCLK_O (TDM Mode Only)

tLROH

LRCLK_O Hold from SCLK_O (TDM Mode Only)

tSOH

SCLK_O Pulsewidth High

tSOL

SCLK_O Pulsewidth Low

tRSTL

RESET Pulsewidth Low

200

NOTES

1Refer to Timing Diagrams section.

2The maximum possible sample rate is: FS

MAX = fMCLK /138.

MCLK of up to 34 MHz is possible under the following conditions: 0

°C < T

A < 70

°C, 45/55 or better MCLK_IN duty cycle.

Specifications subject to change without notice.

TIMING DIAGRAMS

tLRIS

tSIH

tDIS

tSIL

tDIH

tLROS

tSOH

tDOPD

tSOL

tDOH

tLROH

tTDMS

tTDMH

LRCLK_I

SCLK I

SDATA I

LRCLK O

SCLK O

SDATA O

LRCLK O

SCLK O

TDM IN

Figure 1. Input and Output Serial Port Timing (SCLK_I/O,

LRCLK_I/O, SDATA_I/O, TDM_IN)

tRSTL

MCLK IN

RESET

Figure 2.

RESET Timing

tMPWH

tMPWL

Figure 3. MCLK_IN Timing

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