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AD73422

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PBGA BALL CONFIGURATION DESCRIPTIONS (Continued)

BGA

Mnemonic

Location

Function

IRQL0/

(Input) Level-Sensitive Interrupt Requests

PF5

(Input/Output) Programmable I/O Pin.

IRQE/

(Input) Edge-Sensitive Interrupt Requests

PF4

(Input/Output) Programmable I/O Pin.

PF3

(Input/Output) Programmable I/O Pin During Normal Operation.

Mode C/

(Input) Mode Select Input—Checked Only During RESET.

PF2

(Input/Output) Programmable I/O Pin During Normal Operation.

Mode B/

(Input) Mode Select Input—Checked Only During RESET.

PF1

(Input/Output) Programmable I/O Pin During Normal Operation.

Mode A/

(Input) Mode Select Input—Checked Only During RESET.

PF0

(Input/Output) Programmable I/O Pin During Normal Operation.

CLKIN

(Inputs) Clock or Quartz Crystal Input. The CLKIN input cannot be halted or changed during operation

XTAL

nor operated below 10 MHz during normal operation.

CLKOUT

(Output) Processor Clock Output.

SPORT0

TFS0

(Input/Output) SPORT0 Transmit Frame Sync.

RFS0

(Input/Output) SPORT0 Receive Frame Sync.

DT0

(Output) SPORT0 Transmit Data.

DR0

(Input) SPORT0 Receive Data.

SCLK0

(Input/Output) SPORT0 Serial Clock.

SPORT1

TFS1/

(Input/Output) SPORT1 Transmit Frame Sync.

IRQ1

(Input) Edge or Level Sensitive Interrupt.

RFS1

(Input/Output) SPORT1 Receive Frame Sync.

IRQ0

(Input) Edge or Level Sensitive Interrupt.

DT1/

(Output) SPORT1 Transmit Data.

(Output) Flag Out

DR1/

(Input) SPORT1 Receive Data.

(Input) Flag In

SCLK1

(Input/Output) SPORT1 Serial Clock.

FL0

(Output) Flag 0.

FL1

(Output) Flag 1.

FL2

(Output) Flag 2.

VDD(INT)

(Input) DSP Core Supply.

VDD(EXT)

(Input) DSP I/O Interface Supply.

GND

DSP Ground.

EZ-ICE Port

ERESET

EMS

ECLK

ELOUT

ELIN

EINT

EBR

EBG

Address Bus

A0–E7; A1/IAD0–E6; A2/IAD1–E5; A3/IAD2–E4; A4/IAD3–A7; A5/IAD4–B7; A6/IAD5–D7; A7/IAD6–A6;

A8/IAD7–B6; A9/IAD8–C6; A10/IAD9–D6; A11/IAD10–A5; A12/IAD11–B5; A13/IAD12–C5

Data Bus

D0/IAD13–P2; D1/IAD14–N2; D2/IAD15–M2; D3/IACK–L2; D4/IS–M3; D5/IAL–L3; D6/IRD–N4; D7/IWR–

M4; D8–L4; D9–L5; D10–N6; D11–M6; D12–L6; D13–N7; D14–M7; D15–L7; D16–K7; D17–K6; D18–K5;

D19–K4; D20–J7; D21–J6; D22–J5; D23–J4

NOTES

1Interrupt/Flag pins retain both functions concurrently. If IMASK is set to enable the corresponding interrupts, then the DSP will vector to the appropriate interrupt

vector address when the pin is asserted, either by external devices, or set as a programmable flag.

2SPORT configuration determined by the DSP System Control Register. Software configurable.

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