AD73422 datasheet(27/36 Pages) AD

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AD73422

–27–

MEMORY ARCHITECTURE

The AD73422 provides a variety of memory and peripheral

interface options. The key functional groups are Program

Memory, Data Memory, Byte Memory and I/O. Refer to the

following figures and tables for PM and DM memory alloca-

tions in the AD73422.

PROGRAM MEMORY

Program Memory (Full Memory Mode)

is a 24-bit-wide

space for storing both instruction op codes and data. The

AD73422-80 has 16K words of Program Memory RAM on chip

(the AD73422-40 has 8K words of Program Memory RAM on

chip), and the capability of accessing up to two 8K external

memory overlay spaces using the external data bus.

Program Memory (Host Mode)

allows access to all internal

memory. External overlay access is limited by a single external

address line (A0). External program execution is not available in

host mode due to a restricted data bus that is 16 bits wide only.

Table XXII. PMOVLAY Bits

PMOVLAY

Memory

A13

A12:0

Internal

Not Applicable Not Applicable

External

13 LSBs of Address

Overlay 1

Between 0x2000

and 0x3FFF

External

13 LSBs of Address

Overlay 2

Between 0x2000

and 0x3FFF

ACCESSIBLE WHEN

PMOVLAY = 2

ACCESSIBLE WHEN

PMOVLAY = 1

ALWAYS

ACCESSIBLE

AT ADDRESS

0x0000 – 0x1FFF

ACCESSIBLE WHEN

PMOVLAY = 0

PM (MODE B = 0)

INTERNAL

MEMORY

EXTERNAL

MEMORY

0x2000–

0x3FFF

0x2000–

0x3FFF2

0x2000–

0x3FFF2

8K INTERNAL

PMOVLAY = 0

8K EXTERNAL

PROGRAM MEMORY

MODE B = 1

ADDRESS

0x3FFF

0x2000

0x1FFF

0x0000

8K INTERNAL

PMOVLAY = 0

8K EXTERNAL

PMOVLAY = 1 OR 2

0x3FFF

0x2000

0x1FFF

8K INTERNAL

0x0000

PROGRAM MEMORY

MODE B = 0

ADDRESS

ACCESSIBLE WHEN

PMOVLAY = 0

INTERNAL

MEMORY

EXTERNAL

MEMORY

0x2000–

0x3FFF

0x0000–

0x1FFF2

PM (MODE B = 1)1

RESERVED

1WHEN MODE B = 1, PMOVLAY MUST BE SET TO 0

2SEE TABLE III FOR PMOVLAY BITS

ACCESSIBLE WHEN

PMOVLAY = 0

RESERVED

Figure 15. Program Memory Map

DATA MEMORY

Data Memory (Full Memory Mode)

is a 16-bit-wide space

used for the storage of data variables and for memory-mapped

control registers. The AD73422-80 has 16K words on Data

Memory RAM on chip (the AD73422-40 has 8K words on Data

Memory RAM on chip), consisting of 16,352 user-accessible

locations in the case of the AD73422-80 (8,160 user-accessible

locations in the case of the AD73422-40) and 32 memory-

mapped registers. Support also exists for up to two 8K external

memory overlay spaces through the external data bus. All inter-

nal accesses complete in one cycle. Accesses to external memory

are timed using the wait states specified by the DWAIT register.

ACCESSIBLE WHEN

DMOVLAY = 2

ACCESSIBLE WHEN

DMOVLAY = 1

ALWAYS

ACCESSIBLE

AT ADDRESS

x2000 – 0x3FFF

ACCESSIBLE WHEN

DMOVLAY = 0

INTERNAL

MEMORY

EXTERNAL

MEMORY

x0000–

x1FFF

x0000–

x1FFF

x0000–

x1FFF

DATA MEMORY

32 MEMORY

MAPPED

REGISTERS

x3FFF

x2000

x1FFF

INTERNAL

8160

WORDS

x0000

DATA MEMORY

ADDRESS

8K INTERNAL

DMOVLAY = 0

EXTERNAL 8K

DMOVLAY = 1, 2

x3FE0

x3FDF

Figure 16. Data Memory Map

Data Memory (Host Mode) allows access to all internal memory.

External overlay access is limited by a single external address

line (A0). The DMOVLAY bits are defined in Table XXIII.

Table XXIII. DMOVLAY Bits

DMOVLAY

Memory

A13

A12:0

Internal

Not Applicable Not Applicable

External

13 LSBs of Address

Overlay 1

Between 0x2000

and 0x3FFF

External

13 LSBs of Address

Overlay 2

Between 0x2000

and 0x3FFF

I/O Space (Full Memory Mode)

The AD73422 supports an additional external memory space

called I/O space. This space is designed to support simple con-

nections to peripherals (such as data converters and external

registers) or to bus interface ASIC data registers. I/O space

supports 2048 locations of 16-bit wide data. The lower eleven

bits of the external address bus are used; the upper three bits are

undefined. Two instructions were added to the core ADSP-2100

Family instruction set to read from and write to I/O memory

space. The I/O space also has four dedicated 3-bit wait state

registers, IOWAIT0-3, that specify up to seven wait states to be

automatically generated for each of four regions. The wait states

act on address ranges as shown in Table XXIV.

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