AD73422 datasheet(3/36 Pages) AD

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REV. 0

–3–

AD73422

Parameter

Min

Typ

Max

Units

Test Conditions

DAC SPECIFICATIONS

Maximum Voltage Output Swing

Single-Ended

1.578

V p-p

PGA = 6 dB

–2.85

dBm

Max Output = (1.578/1.25)

× VREFCAP

Differential

3.156

V p-p

PGA = 6 dB

3.17

dBm

Max Output = 2

× ((1.578/1.25) × VREFCAP)

Nominal Voltage Output Swing (0 dBm0)

Single-Ended

1.0954

V p-p

PGA = 6 dB

–6.02

dBm

Differential

2.1909

V p-p

PGA = 6 dB

dBm

Output Bias Voltage

1.2

REFOUT Unloaded

Absolute Gain

–0.85 +0.4

+0.85

1.0 kHz, 0 dBm0; Unloaded

Gain Tracking Error

±0.1

1.0 kHz, +3 dBm0 to –50 dBm0

Signal to (Noise + Distortion) at 0 dBm0

PGA = 6 dB

62.5

300 Hz to 3400 Hz; fSAMP = 64 kHz

Total Harmonic Distortion at 0 dBm0

PGA = 6 dB

–80

–62.5

300 Hz to 3400 Hz; fSAMP = 64 kHz

Intermodulation Distortion

–85

PGA = 0 dB

Idle Channel Noise

–85

dBm0

PGA = 0 dB

Crosstalk, DAC-to-ADC

–90

ADC Input Level: AGND;

DAC Output Level: 1.0 kHz, 0 dBm0;

Input Amplifiers Bypassed

–77

Input Amplifiers Included in Input Channel

DAC-to-DAC

–100

DAC1 Output Level: AGND;

DAC2 Output Level: 1.0 kHz, 0 dBm0

Power Supply Rejection

–65

Input Signal Level at AVDD and DVDD

Pins: 1.0 kHz, 100 mV p-p Sine Wave

Group Delay

4, 5

µs

Interpolator Bypassed

µs

Output DC Offset

2, 7

–20

+20

+60

Minimum Load Resistance, RL

2, 8

Single-Ended

600

Ω

Differential

600

Ω

Maximum Load Capacitance, CL

2, 8

Single-Ended4

500

Differential

100

LOGIC INPUTS

VINH, Input High Voltage

DVDD – 0.8

DVDD V

VINL, Input Low Voltage

0.8

IIH, Input Current

–10

+10

µA

CIN, Input Capacitance

LOGIC OUTPUT

VOH, Output High Voltage

DVDD – 0.4

DVDD V

|IOUT|

≤ 100 µA

VOL, Output Low Voltage

0.4

|IOUT|

≤ 100 µA

Three-State Leakage Current

–10

+10

µA

POWER SUPPLIES

AVDD

3.0

3.6

DVDD

3.0

3.6

IDD

See Table I

NOTES

1 Operating temperature range is as follows: –20

°C to +85°C; therefore, T

MIN = –20

°C and T

MAX = +85

°C.

2 Test conditions: Input PGA set for 0 dB gain, Output PGA set for 6 dB gain, no load on analog outputs (unless otherwise noted).

3 At input to sigma-delta modulator of ADC.

4 Guaranteed by design.

5 Overall group delay will be affected by the sample rate and the external digital filtering.

6 The ADC’s input impedance is inversely proportional to DMCLK and is approximated by: (3.3

× 1011)/DMCLK.

7 Between VOUTP1 and VOUTN1 or between VOUTP2 and VOUTN2.

8 At VOUT output.

9 Frequency responses of ADC and DAC measured with input at audio reference level (the input level that produces an output level of –10 dBm0), with 38 dB pream-

plifier bypassed and input gain of 0 dB.

10 Test Conditions: no load on digital inputs, analog inputs ac-coupled to ground, no load on analog outputs.

Specifications subject to change without notice.

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