AD73422 datasheet(12/36 Pages) AD

12 / 36 page

REV. 0

AD73422

–12–

Decimation Filter

The digital filter used in the AD73422’s AFE section carries out

two important functions. Firstly, it removes the out-of-band

quantization noise, which is shaped by the analog modulator,

and secondly, it decimates the high frequency bitstream to a

lower rate 16-bit word.

The antialiasing decimation filter is a sinc-cubed digital filter

that reduces the sampling rate from DMCLK/8 to DMCLK/

256, and increases the resolution from a single bit to 15 bits or

greater (depending on chosen sampling rate). Its Z transform is

given as: [(1–Z

–N)/(1–Z–1)]3 where N is set by the sampling rate

(N = 32 @ 64 kHz sampling . . . N = 256 @ 8 kHz sampling)

Thus when the sampling rate is 64 kHz a minimal group delay

of 25

µs can be achieved.

Word growth in the decimator is determined by the sampling

rate. At 64 kHz sampling, where the oversampling ratio between

sigma-delta modulator and decimator output equals 32, we get

five bits per stage of the three stage Sinc3 filter. Due to symme-

try within the sigma-delta modulator, the LSB will always be a

zero, therefore the 16-bit ADC output word will have 2 LSBs

equal to zero, one due to the sigma-delta symmetry and the

other being a padding zero to make up the 16-bit word. At

lower sampling rates, decimator word growth will be greater

than the 16-bit sample word, therefore truncation occurs in

transferring the decimator output as the ADC word. For example

at 8 kHz sampling, word growth reaches 24 bits due to the OSR

of 256 between sigma-delta modulator and decimator output.

This yields eight bits per stage of the 3-stage Sinc3 filter.

ADC Coding

The ADC coding scheme is in twos complement format (see

Figure 6). The output words are formed by the decimation

filter, which grows the word length from the single-bit output of

the sigma-delta modulator to a word length of up to 18 bits

(depending on decimation rate chosen), which is the final out-

put of the ADC block. In Data Mode this value is truncated to

16 bits for output on the Serial Data Output (SDO) pin. For

input values equal to or greater than positive full scale, however,

VREF

VFBP

VFBN

ANALOG

INPUT

VREF + (VREF

0.32875)

VREF – (VREF

0.32875)

ANALOG

INPUT

VREF + (VREF

0.6575)

VREF – (VREF

0.6575)

VFBP

VFBN

10...00

00...00

01...11

ADC CODE DIFFERENTIAL

10...00

00...00

01...11

ADC CODE SINGLE-ENDED

VREF

Figure 6. ADC Transfer Function

the output word is set at 0x7FFF, which has the LSB set to 1.

In mixed Control/Data Mode, the resolution is fixed at 15 bits,

with the MSB of the 16-bit transfer being used as a flag bit to

indicate either control or data in the frame.

Decoder Channel

The decoder channels consist of digital interpolators, digital

sigma-delta modulators, single bit digital-to-analog converters

(DAC), analog smoothing filters and programmable gain ampli-

fiers with differential outputs.

DAC Coding

The DAC coding scheme is in twos complement format with

0x7FFF being full-scale positive and 0x8000 being full-scale

negative.

Interpolation Filter

The anti-imaging interpolation filter is a sinc-cubed digital filter

that up-samples the 16-bit input words from the input sample

rate to a rate of DMCLK/8, while filtering to attenuate images

produced by the interpolation process. Its’ Z transform is given

as: [(1–Z

–N)/(1–Z–1)]3 where N is determined by the sampling

rate (N = 32 @ 64 kHz . . . N = 256 @ 8 kHz). The DAC re-

ceives 16-bit samples from the host DSP processor at the pro-

grammed sample rate of DMCLK/N. If the host processor fails

to write a new value to the serial port, the existing (previous)

data is read again. The data stream is filtered by the anti-imaging

interpolation filter, but there is an option to bypass the interpo-

lator for the minimum group delay configuration by setting the

IBYP bit (CRE:5) of Control Register E. The interpolation filter

has the same characteristics as the ADC’s antialiasing decima-

tion filter.

The output of the interpolation filter is fed to the DAC’s digital

sigma-delta modulator, which converts the 16-bit data to 1-bit

samples at a rate of DMCLK/8. The modulator noise-shapes

the signal so that errors inherent to the process are minimized in

the passband of the converter. The bitstream output of the

sigma-delta modulator is fed to the single bit DAC where it is

converted to an analog voltage.

Analog Smoothing Filter and PGA

The output of the single-bit DAC is sampled at DMCLK/8,

therefore it is necessary to filter the output to reconstruct the

low frequency signal. The decoder’s analog smoothing filter

consists of a continuous-time filter preceded by a third-order

switched-capacitor filter. The continuous-time filter forms part

of the output programmable gain amplifier (PGA). The PGA

can be used to adjust the output signal level from –15 dB to

+6 dB in 3 dB steps, as shown in Table II. The PGA gain is

set by bits OGS0, OGS1 and OGS2 (CRD:4-6) in Control

Table II. PGA Settings for the Decoder Channel

OGS2

OGS1

OGS0

Gain (dB)

000

001

010

011

–3

100

–6

101

–9

110

–12

111

–15

AD73422 Datasheet(PDF) 12 Page - Analog Devices

AD73422 Datasheet(HTML) 12 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 26 27 28 29 30 31 32 33 34 35 36

Datasheet Download

Link URL