AD73422 datasheet(13/36 Pages) AD

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AD73422

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Differential Output Amplifiers

The decoder has a differential analog output pair (VOUTP and

VOUTN). The output channel can be muted by setting the

MUTE bit (CRD:7) in Control Register D. The output signal is

dc-biased to the codec’s on-chip voltage reference.

Voltage Reference

The AD73422 reference, REFCAP, is a bandgap reference that

provides a low noise, temperature-compensated reference to the

DAC and ADC. A buffered version of the reference is also made

available on the REFOUT pin and can be used to bias other

external analog circuitry. The reference has a nominal value of

1.2 V.

The reference output (REFOUT) can be enabled for biasing

external circuitry by setting the RU bit (CRC:6) of CRC.

INVERTING

OP AMPS

ANALOG

LOOP-BACK

SELECT

INVERT

CONTINUOUS

TIME

LOW-PASS

FILTER

VREF

VFBN1

VINN1

VINP1

VFBP1

VOUTP1

VOUTN1

REFCAP

REFOUT

AD73422

AFE SECTION

VREF

ANALOG

GAIN TAP

GAIN

+6/–15dB

PGA

REFERENCE

SINGLE-ENDED

ENABLE

0/38dB

PGA

Figure 7. Analog Input/Output Section

Analog and Digital Gain Taps

The AD73422 features analog and digital feedback paths be-

tween input and output. The amount of feedback is determined

by the gain setting that is programmed in the control registers.

This feature can typically be used for balancing the effective

impedance between input and output when used in Subscriber

Line Interface Circuit (SLIC) interfacing.

Analog Gain Tap

The analog gain tap is configured as a programmable differential

amplifier whose input is taken from the ADC’s input signal

path. The output of the analog gain tap is summed with the

output of the DAC. The gain is programmable using Control

with muting being achieved through a separate control setting

(Control Register F Bit _). The gain increment per step is 0.0625.

The AGT is enabled by powering up the AGT control bit in the

power control register (CRC:1). When this bit is set (=1) CRF

becomes an AGT control register with CRF:0-4 holding the

AGT coefficient, CRF:5 becomes an AGT enable and CRF:7

becomes an AGT mute control bit. Control bit CRF:5 connects/

disconnects the AGT output to the summer block at the output

of the DAC section while control bit CRF:7 overrides the gain

tap setting with a mute, or zero gain, setting (which is omitted

from the gain settings). Table III shows the gain versus digital

setting for the AGT.

Table III. Analog Gain Tap Settings*

AGTC4

AGTC3

AGTC2

AGTC1 AGTC0

Gain

+1.00

+0.9375

+0.875

+0.8125

+0.075

——

—

+0.0625

–0.0625

——

—

–0.875

–0.9375

–1.00

*AGE and DGT weights are given for the case of VFBNx (connected to the

sigma-delta modulator’s positive input) being at a higher potential than VFBPx

(connected to the sigma-delta modulator’s negative input).

Digital Gain Tap

The digital gain tap features a programmable gain block whose

input is taken from the bitstream from the ADC’s sigma-delta

modulator. This single bit input (1 or 0) is used to add or sub-

tract a programmable value, which is the digital gain tap setting,

to the output of the DAC section’s interpolator. The program-

mable setting has 16-bit resolution and is programmed using the

settings in Control Registers G and H.

Table IV. Digital Gain Tap Settings*

DGT15-0 (Hex)

Gain

0x8000

–1.00

0x9000

–0.875

0xA000

–0.75

0xC000

–0.5

0xE000

–0.25

0x0000

–0.00

0x2000

+0.25

0x4000

+0.5

0x6000

+0.75

0x7FFF

+0.99999

*AGE and DGT weights are given for the case of VFBNx (connected to the

sigma-delta modulator’s positive input) being at a higher potential than VFBPx

(connected to the sigma-delta modulator’s negative input).

AFE Serial Port (SPORT2)

The AFE section communicates with the DSP section via its

bidirectional synchronous serial port (SPORT2), which interfaces

to either SPORT0 or SPORT1 of the DSP section. SPORT2 is

used to transmit and receive digital data and control informa-

tion. The dual AFE is implemented using two separate AFE

blocks that are internally cascaded with serial port access to the

input of AFE Channel 1 and the output of AFE Channel 2.

This allows other single or dual codec devices to be cascaded

together (up to a limit of eight codec units).

In both transmit and receive modes, data is transferred at the

serial clock (SCLK2) rate with the MSB being transferred first.

Communications between the AFE section and the DSP section

must always be initiated by the AFE section (AFE is in master

mode—DSP SPORT is in slave mode). This ensures that there

is no collision between input data and output samples.

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