REV. 0

AD7398/AD7399

–5–

PIN CONFIGURATION

TOP VIEW

(Not to Scale)

AD7398/

AD7399

CLK

GND

CS

SDI

LDAC

RS

16

15

14

13

12

11

10

9

8

7

6

5

4

3

2

1

PIN FUNCTION DESCRIPTIONS

Pin No.

Mnemonic

Function

DAC B Voltage Output.

DAC A Voltage Output.

Negative Power Supply Input. Specified range of operation 0 V to –5.5 V.

DAC A Reference Voltage Input Terminal. Establishes DAC A full-scale output voltage. Pin can

DAC B Reference Voltage Input Terminal. Establishes DAC B full-scale output voltage. Pin can

6

GND

Ground Pin.

7

LDAC

Load DAC Register Strobe, Level Sensitive Active Low. Transfers all Input Register data to

DAC registers. Asynchronous active low input. See Control Logic Truth Table for operation.

8

RS

Resets Input and DAC Registers to All Zero Codes. Shift Register contents unchanged.

9

CS

Chip Select, Active Low Input. Disables shift register loading when high. Transfers Serial Regis-

ter Data to the Input Register when

CS returns High. Does not effect LDAC operation.

10

CLK

Schmitt Triggered Clock Input, Positive Edge Clocks Data into Shift Register.

11

SDI

Serial Data Input. Input data loads directly into the shift register.

12

DAC D Reference Voltage Input Terminal. Establishes DAC D full-scale output voltage. Pin can

13

DAC C Reference Voltage Input Terminal. Establishes DAC C full-scale output voltage. Pin can

14

Positive Power Supply Input. Specified range of operation 3 V to 5 V

± 10%.

15

DAC D Voltage Output.

16

DAC C Voltage Output.