AD7398 datasheet(6/16 Pages) AD

6 / 16 page

REV. 0

AD7398/AD7399

–6–

Table I. Control Logic Truth Table

CLK

LDAC

Serial Shift Register Function

Input Register Function

DAC Register

No Effect

↑+

Shift-Register-Data Advanced One Bit

Latched

No Effect

Latched

↑+

L/H

No Effect

Updated with SR Contents

Latched

No Effect

Latched

Transparent

↑+

No Effect

Latched

NOTES

↑+ Positive logic transition; ↓– Negative logic transition; X Don’t Care; SR shift register.

2. At power ON, both the Input Register and the DAC Register are loaded with all zeros.

. During Power Shutdown, reprogramming of any internal registers can take place, but the output amplifiers will not produce the new values until the part is taken

out of Shutdown mode.

LDAC input is a level-sensitive input that controls the four DAC registers.

Table II. AD7398 Serial Input Register Data Format, Data Is Loaded in the MSB-First Format

MSB

LSB

Bit Position B15

B14

B13

B12

B11

B10

AD7398

D11

D10

NOTE

Bit positions B14 and B15 are power shutdown control Bits SD and SA. If SA is set to Logic 1, all DACs are placed in the power shutdown mode. If SD is set to

Logic 1, the address decoded by Bits B12 and B13 (A0 and A1) determine the DAC channel that will be placed in the power shutdown state.

Table III. AD7399 Serial Input Register Data Format, Data Is Loaded in the MSB-First Format

MSB

LSB

Bit Position B13

B12

B11

B10

AD7399

NOTE

Bit positions B12 and B13 are power shutdown control Bits SD and SA. If SA is set to Logic 1, all DACs are placed in the power shutdown mode. If SD is set to

Logic 1, the address decoded by Bits B10 and B11 (A0 and A1) determine the DAC channel that will be placed in the power shutdown state.

Table IV. AD7398/AD7399 Address Decode Control

DAC Channel Affected

All DACs Shutdown

0100

DAC A Shutdown

0101

DAC B Shutdown

0110

DAC C Shutdown

0111

DAC D Shutdown

0000

DAC A Input Register Decoded

0001

DAC B Input Register Decoded

0010

DAC C Input Register Decoded

0011

DAC D Input Register Decoded

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