REV. 0

AD7398/AD7399

–14–

80C51/80L51 to AD7398/AD7399 Interface

A serial interface between the AD7398/AD7399 and the 80C51/

80L51 microcontroller is shown in Figure 11. TxD of the micro-

controller drives the CLK of the AD7398/AD7399, while RxD

drives the serial data line of the DAC. P3.3 is a bit program-

mable pin on the serial port which is used to drive

CS.

CLK

SDI

CS

LDAC

AD7398/

AD7399

*ADDITIONAL PINS OMITTED FOR CLARITY

80C51/

80L51*

P3.4

P3.3

Figure 11. 80C51/80L51 to AD7398/AD7399 Interface

Note that the 80C51/80L51 provides the LSB first, while the

AD7398/AD7399 expect the MSB of the 16-bit/14-bit word

first. Care should be taken to ensure the transmit routine takes

this into account. It can usually be done through software by

shifting out and accumulating the bits in the correct order

before inputting to the DAC. In addition, 80C51 outputs two

byte words/16 bits data, thus for AD7399, the first two bits,

after rearrangement, should be Don’t Care as they will be

dropped from the AD7399’s 14-bit word.

When data is to be transmitted to the DAC, P3.3 is taken low.

Data on RxD is valid on the falling edge of TxD, so the clock

must be inverted as the DAC clocks data into the input shift

register on the rising edge of the serial clock. The 80C51/80L51

transmits its data in 8-bit bytes with only eight falling clock edges

occurring in the transmit cycle. As AD7399 requires a 14-bit

word, P3.3 (or any one of the other programmable bits) is the

CS

input signal to the DAC, so P3.3 should be brought low at the

beginning of the 16-bit write cycle 2

× 8 bit words, and held low

until the 16-bit 2

× 8 cycle is completed. After that, P3.3 is

brought high again and the new data loads to the DAC. Again,

the first two bits, after rearranging, should be don’t care.

LDAC

on the AD7398/AD7399 may also be controlled by the 80C51/

80L51 serial port output by using another bit-programmable

pin, P3.4.

ADSP-2101/ADSP-2103 to AD7398/AD7399 Interface

Figure 8 shows a serial interface between the AD7398/AD7399

and the ADSP-2101/ADSP-2103. The ADSP-2101/ADSP-2103

is set to operate in the SPORT (Serial Port) transmit alternate

framing mode. The ADSP-2101/ADSP-2103 is programmed

through the SPORT control register and should be configured

as follows: Internal Clock Operation, Active Low Framing,

16-Bit-Word Length. For the AD7398, transmission is initiated

by writing a word to the Tx register after the SPORT has been

enabled. For the AD7399, the first two bits are don’t care as the

AD7399 will keep the last 14 bits. Similarly, transmission is

initiated by writing a word to the Tx register after the SPORT

has been enabled. Because of the edge-triggered difference, an

inverter is required at the SCLKs between the DSP and the DAC.

CLK

SDI

CS

LDAC

AD7398/

AD7399

*ADDITIONAL PINS OMITTED FOR CLARITY

ADSP-2101/

ADSP-2103*

SCLK

DT

FO

TFS

Figure 8. ADSP-2101/ADSP-2103 to AD7398/AD7399

Interface

68HC11 to AD7398/AD7399 Interface

Figure 9 shows a serial interface between the AD7398/AD7399

and the 68HC11 microcontroller. SCK of the 68HC11 drives

the CLK of the DAC, while the MOSI output drives the serial

data lines SDI.

CS signal is driven from one of the port lines.

The 68HC11 is configured for master mode; MSTR = 1, CPOL = 0,

and CPHA = 0. Data appearing on the MOSI output is valid on

the rising edge of SCK.

CLK

SDI

CS

LDAC

AD7398/

AD7399

*ADDITIONAL PINS OMITTED FOR CLARITY

68HC11/

68L11*

SCK

MOS1

PC6

PC7

Figure 9. 68HC11/68L11 to AD7398/AD7399 Interface

MICROWIRE to AD7398/AD7399 Interface

Figure 10 shows an interface between the AD7398/AD7399 and

any MICROWIRE-compatible device. Serial data is shifted out

on the falling edge of the serial clock and into the AD7398/

AD7399 on the rising edge of the serial clock. No glue logic is

required as the DAC clocks data into the input shift register on

the rising edge.

CLK

SDI

CS

AD7398/

AD7399

*ADDITIONAL PINS OMITTED FOR CLARITY

MICROWIRE*

SCK

SO

CS

Figure 10. MICROWIRE to AD7398/AD7399 Interface