AD7710 datasheet(5/28 Pages) AD

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AD7710

REV. F

–5–

(DVDD = +5 V

5%; AVDD = +5 V or +10 V

5%; VSS = 0 V or –5 V

10%; AGND = DGND =

0 V; fCLK IN =10 MHz; Input Logic 0 = 0 V, Logic 1 = DVDD, unless otherwise noted)

TIMING CHARACTERISTICS1, 2

Limit at TMIN, TMAX

Parameter

(A, S Versions)

Units

Conditions/Comments

fCLK IN

4, 5

Master Clock Frequency: Crystal Oscillator or Externally

400

kHz min

Supplied for Specified Performance

MHz max

AVDD = +5 V

± 5%

MHz max

AVDD = +5.25 V to +10.5 V

tCLK IN LO

0.4

× t

CLK IN

ns min

Master Clock Input Low Time. tCLK IN = 1/fCLK IN

tCLK IN HI

0.4

× t

CLK IN

ns min

Master Clock Input High Time

ns max

Digital Output Rise Time. Typically 20 ns

ns max

Digital Output Fall Time. Typically 20 ns

1000

ns min

SYNC Pulsewidth

Self-Clocking Mode

ns min

DRDY to RFS Setup Time

ns min

DRDY to RFS Hold Time

× t

CLK IN

ns min

A0 to

RFS Setup Time

ns min

A0 to

RFS Hold Time

× t

CLK IN + 20

ns max

RFS Low to SCLK Falling Edge

× t

CLK IN + 20

ns max

Data Access Time (

RFS Low to Data Valid)

tCLK IN/2

ns min

SCLK Falling Edge to Data Valid Delay

tCLK IN/2 + 30

ns max

tCLK IN/2

ns nom

SCLK High Pulsewidth

t10

× t

CLK IN/2

ns nom

SCLK Low Pulsewidth

t14

ns min

A0 to

TFS Setup Time

t15

ns min

A0 to

TFS Hold Time

t16

× t

CLK IN + 20

ns max

TFS to SCLK Falling Edge Delay Time

t17

× t

CLK IN

ns min

TFS to SCLK Falling Edge Hold Time

t18

ns min

Data Valid to SCLK Setup Time

t19

ns min

Data Valid to SCLK Hold Time

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