AD7710 datasheet(21/28 Pages) AD

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AD7710

REV. F

–21–

Read Operation

As with the self-clocking mode, data can be read from either the

output register, the control register or the calibration registers.

A0 determines whether the data read accesses data from the

control register or from the output/calibration registers. This A0

signal must remain valid for the duration of the serial read

operation. With A0 high, data is accessed from either the output

accessed from the control register.

The function of the

DRDY line is dependent only on the output

update rate of the device and the reading of the output data

DRDY goes low when a new data word is available in

the output data register. It is reset high when the last bit of data

(either 16th bit or 24th bit) is read from the output register. If

data is not read from the output register, the

DRDY line will

remain low. The output register will continue to be updated at

the output update rate but

DRDY will not indicate this. A read

from the device in this circumstance will access the most recent

word in the output register. If a new data word becomes avail-

able to the output register while data is being read from the

output register,

DRDY will not indicate this and the new data

word will be lost to the user.

DRDY is not affected by reading

from the control register or the calibration register.

Data can only be accessed from the output data register when

DRDY is low. If RFS goes low while DRDY is high, no data

transfer will take place.

DRDY does not have any effect on read-

ing data from the control register or from the calibration

registers.

Write Operation

Data can be written to either the control register or calibration

registers. In either case, the write operation is not affected by

the

DRDY line and the write operation does not have any effect

on the status of

DRDY. A write operation to the control register

or the calibration register must always write 24 bits to the re-

spective register.

Figure 11 shows a write operation to the AD7710. A0 deter-

mines whether a write operation transfers data to the control

main valid for the duration of the serial write operation. The

falling edge of

TFS enables the internally generated SCLK

output. The serial data to be loaded to the AD7710 must be

valid on the rising edge of this SCLK signal. Data is clocked

into the AD7710 on the rising edge of the SCLK signal with the

MSB transferred first. On the last active high time of SCLK, the

LSB is loaded to the AD7710. Subsequent to the next falling

edge of SCLK, the SCLK output is turned off. (The timing

diagram of Figure 11 assumes a pull-up resistor on the SCLK

line.)

External Clocking Mode

The AD7710 is configured for its external clocking mode by

tying the MODE pin low. In this mode, SCLK of the AD7710

is configured as an input and an external serial clock must be

provided to this SCLK pin. This external clocking mode is

designed for direct interface to systems which provide a serial

clock output that is synchronized to the serial data output,

including microcontrollers such as the 80C51, 87C51, 68HC11

and 68HC05 and most digital signal processors.

SDATA (I)

SCLK (O)

TFS (I)

A0 (I)

t14

t15

t18

t19

t10

t16

MSB

LSB

t17

Figure 11. Self-Clocking Mode, Control/Calibration Register Write Operation

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