AD7710 datasheet(22/28 Pages) AD

22 / 28 page

REV. F

–22–

AD7710

Figures 12a and 12b show timing diagrams for reading from the

AD7710 in the external clocking mode. Figure 12a shows a

situation where all the data is read from the AD7710 in one read

operation. Figure 12b shows a situation where the data is read

from the AD7710 over a number of read operations. Both read

operations show a read from the AD7710’s output data register.

A read from the control register or calibration registers is similar

but in these cases the

DRDY line is not related to the read func-

tion. Depending on the output update rate, it can go low at any

stage in the control/calibration register read cycle without affect-

ing the read and its status should be ignored. A read operation

from either the control or calibration registers must always read

24 bits of data from the respective register.

Figure 12a shows a read operation from the AD7710 where

RFS remains low for the duration of the data word transmission.

With

DRDY low, the RFS input is brought low. The input

SCLK signal should be low between read and write operations.

RFS going low places the MSB of the word to be read on the

serial data line. All subsequent data bits are clocked out on a

high to low transition of the serial clock and are valid prior to

the following rising edge of this clock. The penultimate falling

edge of SCLK clocks out the LSB and the final falling edge

resets the

DRDY line high. This rising edge of DRDY turns off

the serial data output.

Figure 12b shows a timing diagram for a read operation where

RFS returns high during the transmission of the word and

returns low again to access the rest of the data word. Timing

parameters and functions are very similar to that outlined for

Figure 12a but Figure 12b has a number of additional times to

show timing relationships when

RFS returns high in the middle

of transferring a word.

RFS should return high during a low time of SCLK. On the

rising edge of

RFS, the SDATA output is turned off. DRDY

remains low and will remain low until all bits of the data word

are read from the AD7710, regardless of the number of times

RFS changes state during the read operation. Depending on the

time between the falling edge of SCLK and the rising edge of

RFS, the next bit (BIT N+1) may appear on the databus before

RFS goes high. When RFS returns low again, it activates the

SDATA output. When the entire word is transmitted, the

DRDY line will go high turning off the SDATA output as per

Figure 12a.

RFS (I)

SCLK (I)

SDATA (O)

t24

t 28

LSB

t26

MSB

t 29

THREE-STATE

t 20

A0 (I)

t 22

t23

t 21

t27

t25

DRDY (O)

Figure 12a. External-Clocking Mode, Output Data Read Operation

THREE-STATE

t27

t26

MSB

t30

t 31

BIT N

t24

t25

BIT N+1

SDATA (O)

SCLK (I)

RFS (I)

t20

A0 (I)

DRDY (O)

t22

t25

Figure 12b. External-Clocking Mode, Output Data Read Operation (

RFS Returns High During Read Operation)

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