AD7890 datasheet(12/20 Pages) AD

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AD7890

–12–

REV. A

SCLK

CONVST

CONVERSION IS

INITIATED AND

TRACK/HOLD GOES

INTO HOLD

CONVERSION

ENDS 5.9µs

LATER

SERIAL READ

& WRITE

OPERATIONS

RFS

TFS

NEXT CONVST

RISING EDGE

µP INT

SERVICE OR

POLLING

ROUTINE

500ns MIN

READ & WRITE

OPERATIONS SHOULD

END 500ns PRIOR TO

NEXT RISING EDGE OF

CONVST

CONVERT

Figure 6. CONVST Used as Status Signal in External Clocking Mode

In the Self-Clocking Mode, the AD7890 indicates when conver-

sion is complete by bringing the RFS line low and initiating a

serial data transfer. In the external clocking mode, there is no

indication of when conversion is complete. In many applica-

tions, this will not be a problem as the data can be read from the

part during conversion or after conversion. However, applica-

tions which want to achieve optimum performance from the

AD7890 will have to ensure that the data read does not occur

during conversion or during 500 ns prior to the rising edge of

CONVST

. This can be achieved in either of two ways. The first

is to ensure in software that the read operation is not initiated

until 5.9

µs after the rising edge of CONVST. This will only be

possible if the software knows when the CONVST command is

issued. The second scheme would be to use the CONVST sig-

nal as both the conversion start signal and an interrupt signal.

The simplest way to do this would be to generate a square wave

signal for CONVST with high and low times of 5.9

µs (see Fig-

ure 6). Conversion is initiated on the rising edge of CONVST.

The falling edge of CONVST occurs 5.9

µs later and can be

used as either an active low or falling edge-triggered interrupt

signal to tell the processor to read the data from the AD7890.

Provided the read operation is completed 500 ns before the ris-

ing edge of CONVST, the AD7890 will operate to specification.

This scheme limits the throughput rate to 11.8

µs minimum.

However, depending upon the response time of the micropro-

cessor to the interrupt signal and the time taken by the proces-

sor to read the data, this may the fastest which the system could

have operated. In any case, the CONVST signal does not have

to have a 50:50 duty cycle. This can be tailored to optimize the

throughput rate of the part for a given system.

Alternatively, the CONVST signal can be used as a normal nar-

row pulse width. The rising edge of CONVST can be used as an

active high or rising edge-triggered interrupt. A software delay

of 5.9

µs can then be implemented before data is read from the

part.

CEXT FUNCTIONING

The CEXT input on the AD7890 provides a means of determin-

ing how long after a new channel address is written to the part

that a conversion can take place. The reason behind this is

two-fold. Firstly, when the input channel to the AD7890 is

changed, the input voltage on this new channel is likely to be

very different from the previous channel voltage. Therefore, the

part’s track/hold has to acquire the new voltage before an accu-

rate conversion can take place. An internal pulse delays any con-

version start command (as well as the signal to send the track/

hold into hold) until after this pulse has timed out. The second

reason is to allow the user to connect external antialiasing or sig-

nal conditioning circuitry between MUX OUT and SHA IN.

This external circuitry will introduce extra settling time into the

system. The CEXT pin provides a means for the user to extend

the internal pulse to take this extra settling time into account.

Basically, varying the value of the capacitor on the CEXT pin var-

ies the duration of the internal pulse. Figure 7 shows the rela-

tionship between the value of the CEXT capacitor and the

internal delay.

2000

250

1750

1500

1250

1000

750

500

EXT CAPACITANCE – pF

A = +85 °C

A = –40 °C

A = +25 °C

Figure 7. Internal Pulse Width vs. CEXT

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