AD7890 datasheet(15/20 Pages) AD

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AD7890

–15–

REV. A

SCLK (I)

DATA IN (I)

TFS (I)

STBY

DON'T

CARE

DON'T

CARE

CONV

DON'T

CARE

NOTE

(I) SIGNIFIES AN INPUT; (O) SIGNIFIES AN OUTPUT.

Figure 11. External Clocking (Slave) Mode Control Register Write

SIMPLIFYING THE INTERFACE

To minimize the number of interconnect lines to the AD7890,

the user can connect the RFS and TFS lines of the AD7890

together and read and write from the part simultaneously. In

this case, new control register data should be provided on the

DATA IN line selecting the input channel and possibly provid-

ing a conversion start command while the part provides the

result from the conversion just completed on the DATA OUT

line.

In the self-clocking mode, this means that the part provides all

the signals for the serial interface. It does require that the

microprocessor has the data to be written to the Control

TFS

line low. In the external clocking mode, it means that the

user only has to supply a single frame synchronization signal to

control both the read and write operations.

Care must be taken with this scheme that the read operation is

completed before the next conversion starts if the user wants to

obtain optimum performance from the part. In the case of the

software conversion start, the conversion command is written to

the Control Register on the sixth serial clock edge. However, the

read operation continues for another 10 serial clock cycles. To

avoid reading during the sampling instant or during conversion,

the user should ensure that the internal pulse width is suffi-

ciently long (by choosing CEXT) so that the read operation is

completed before the next conversion sequence begins. Failure

to do this will result in significantly degraded performance from

the part, both in terms of signal-to-noise ratio and dc param-

eters. In the case of a hardware conversion start, the user should

ensure that the delay between the sixth falling edge of the serial

clock in the write operation and the next rising edge of

CONVST

is greater than the internal pulse width.

MICROPROCESSOR/MICROCONTROLLER INTERFACE

The AD7890’s flexible serial interface allows for easy connec-

tion to the serial ports of DSP processors and microcontrollers.

Figures 12 through 15 show the AD7890 interfaced to a num-

ber of different microcontrollers and DSP processors. In some

of the interfaces shown, the AD7890 is configured as the master

in the system, providing the serial clock and frame sync for the

read operation while in others it acts as a slave with these signals

provided by the microprocessor.

AD7890–8051 Interface

Figure 12 shows an interface between the AD7890 and the

8XC51 microcontroller. The AD7890 is configured for its ex-

ternal clocking mode while the 8XC51 is configured for its

Mode 0 serial interface mode. The diagram shown in Figure 12

makes no provisions for monitoring when conversion is complete

on the AD7890 (assuming hardware conversion start is used).

To monitor the conversion time on the AD7890 a scheme such

as outlined previously with CONVST can be used. This can be

implemented in two ways. One is to connect the CONVST line

to another parallel port bit which is configured as an input. This

port bit can then be polled to determine when conversion is

complete. An alternative is to use an interrupt driven system in

which case the CONVST line should be connected to the INT1

input of the 8XC51.

Since the 8XC51 contains only one serial data line, the DATA

OUT and DATA IN lines of the AD7890 must be connected to-

gether. This means that the 8XC51 cannot communicate with

the output register and Control Register of the AD7890 at the

same time. The 8XC51 outputs the LSB first in a write opera-

tion so care should be taken in arranging the data which is to be

transmitted to the AD7890. Similarly, the AD7890 outputs the

MSB first during a read operation while the 8XC51 expects the

LSB first. Therefore, the data that is to be read into the serial

port needs to be rearranged before the correct data word from

the AD7890 is available in the microcontroller.

The serial clock rate from the 8XC51 is limited to significantly

less than the allowable input serial clock frequency with which

the AD7890 can operate. As a result, the time to read data from

the part will actually be longer than the conversion time of the

part. This means that the AD7890 cannot run at its maximum

throughput rate when used with the 8XC51.

SMODE

TFS

DATA OUT

DATA IN

SCLK

AD7890

RFS

P1.0

P1.1

P3.0

P3.1

8XC51

VDD

Figure 12. AD7890 to 8XC51 Interface

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