AD7890 datasheet(17/20 Pages) AD

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AD7890

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REV. A

to which the serial data is referenced, is a delayed version of the

CLK IN signal. The typical delay between the CLK IN and

SCLK is 20 ns and will be no more than 50 ns over supplies and

temperature. Therefore, there will still be sufficient setup time

for DATA OUT to be clocked into the DSP on the edges of the

CLK IN signal. When writing data to the AD7890, the processor’s

data hold time is sufficiently long to cater for the delay between

the two clocks. The AD7890’s RFS signal connects to both the

FSX and FSR inputs of the processor. The processor can gener-

ate its own FSX signal so if required the interface can be modi-

fied so that the RFS and TFS signals are separated and the

processor generates the FSX signal which is connected to the

TFS

input of the AD7890.

In the scheme outlined here, the user does not have to worry

about monitoring the end of conversion. Once conversion is

complete, the AD7890 takes care of transmitting back its con-

version result to the processor. Once the sixteen bits of data

have been received by the processor into its serial shift register,

it generates an internal interrupt. Since RFS and TFS are con-

nected together, data is transmitted to the Control Register of

the AD7890 whenever the AD7890 transmits its conversion

result. The user just has to ensure that the word to be written to

the AD7890 Control Register is set up prior to the end of con-

version. As part of the interrupt routine which recognizes that

data has been read in, the processor can set up the data which it

is going to write to the Control Register next time around.

SMODE

TFS

DATA OUT

DATA IN

SCLK

AD7890

RFS

FSR

CLKX

TMS320C25/C30

CLKR

FSX

CLK INPUT

CLK IN

Figure 16. AD7890 to TMS320C25/30 Interface

ANTIALIASING FILTER

The AD7890 provides separate access to the multiplexer and

ADC via the MUX OUT and SHA IN pins. One of the reasons

for this is to allow the user to implement an antialiasing filter

between the multiplexer and the ADC. Inserting the antialiasing

filter at this point has the advantage that one antialiasing filter

can suffice for all eight channels rather than a separate antialias-

ing filter for each channel if they were to be placed prior to the

multiplexer.

The antialiasing filter inserted between the MUX OUT and

SHA IN pins will generally be a low-pass filter to remove high

frequency signals which could possibly be aliased back in-band

during the sampling process. It is recommended that this filter is

an active filter, ideally with the MUX OUT of the AD7890 driv-

ing a high impedance stage and the SHA IN of the part being

driven from a low impedance stage. This will remove any effects

from the variation of the part’s multiplexer on-resistance with

input signal voltage and will also remove any effects of a high

source impedance at the sampling input of the track/hold. With

an external antialiasing filter in place, the additional settling-

time associated with the filter should be accounted for by using

a larger capacitance on CEXT.

AD7890 PERFORMANCE

Linearity

The linearity of the AD7890 is primarily determined by the

on-chip 12-bit D/A converter. This is a segmented DAC which

is laser trimmed for 12-bit integral linearity and differential lin-

earity. Typical relative numbers for the part are

±1/4 LSB while

the typical DNL errors are

±1/2 LSB.

Noise

In an A/D converter, noise exhibits itself as code uncertainty in

dc applications and as the noise floor (in an FFT, for example)

in ac applications. In a sampling A/D converter like the

AD7890, all information about the analog input appears in the

baseband from dc to 1/2 the sampling frequency. The input

bandwidth of the track/hold exceeds the Nyquist bandwidth

and, therefore, an antialiasing filter should be used to remove

unwanted signals above fS/2 in the input signal in applications

where such signals exist.

Figure 17 shows a histogram plot for 8192 conversions of a dc

input using the AD7890. The analog input was set at the centre

of a code transition. The timing and control sequence used was

as per Figure 5 where the optimum performance of the ADC

was achieved. The same performance will be achieved in self-

clocking mode where the part transmits its data after conversion

is complete. It can be seen that almost all the codes appear in

the one output bin indicating very good noise performance from

the ADC. The rms noise performance for the AD7890-2 for the

above plot was 81

µV. Since the analog input range, and hence

LSB size, on the AD7893-4 is 1.638 times what it is for the

AD7893-2, the same output code distribution results in an out-

put rms noise of 143

µV for the AD7893-4. For the AD7890-10,

with an LSB size eight times that of the AD7890-2, the code distri-

bution represents an output rms noise of 648

µV.

9000

2000

1000

(X–3)

(X–4)

3000

4000

5000

6000

7000

8000

(X+4)

(X+3)

(X+2)

(X+1)

(X–1)

(X–2)

SAMPLING FREQUENCY = 102.4kHz

TA = +25°C

CODE

Figure 17. Histogram of 8192 Conversions of a DC Input

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