AD7890

–13–

REV. A

the part is initiated (on the falling edge of TFS). It starts to

discharge on the sixth falling edge of SCLK in the serial write

nominal trigger point of 2.5 V, the internal pulse is timed out.

The internal pulse is initiated each time a write operation to the

Control Register takes place. As a result, the pulse is initiated

and the conversion process delayed for all software conversion

start commands. For hardware conversion start, it is possible to

separate the conversion start command from the internal pulse.

If the multiplexer output (MUX OUT) is connected directly to

the track/hold input (SHA IN), then no external settling has to

be taken into account by the internal pulse width. In applica-

tions where the multiplexer is switched and conversion is not

initiated until more than 2

µs after the channel is changed (as is

possible with a hardware conversion start), the user does not

pin. The 2

µs equates to the track/hold acquisition time of the

AD7890. In applications where the multiplexer is switched and

conversion is initiated at the same time (such as with a software

conversion start), a 120 pF capacitor should be connected to

conversion is initiated.

If external circuitry is connected between MUX OUT and SHA

IN, then the extra settling time introduced by this circuitry will

have to be taken into account. In the case where the multiplexer

change command and the conversion start command are sepa-

rated, they need to be separated by greater than the acquisition

time of the AD7890 plus the settling time of the external cir-

tance. In applications where the multiplexer is switched and

conversion is initiated at the same time (such as with a software

acquisition time of the track/hold plus the settling-time of the

external circuitry before conversion is initiated.

SERIAL INTERFACE

The AD7890’s serial communications port provides a flexible

arrangement to allow easy interfacing to industry-standard

microprocessors, microcontrollers and digital signal processors.

A serial read to the AD7890 accesses data from the output reg-

ister via the DATA OUT line. A serial write to the AD7890

writes data to the Control Register via the DATA IN line.

Two different modes of operation are available, optimized for

different types of interface where the AD7890 can act either as

master in the system (it provides the serial clock and data fram-

ing signal) or acts as slave (an external serial clock and framing

signal can be provided to the AD7890). These two modes,

labelled Self-Clocking Mode and External Clocking Mode, are

discussed in detail in the following sections.

Self-Clocking Mode

The AD7890 is configured for its Self-Clocking Mode by tying

the SMODE pin of the device to a logic low. In this mode, the

AD7890 provides the serial clock signal and the serial data

framing signal used for the transfer of data from the AD7890.

This Self-Clocking Mode can be used with processors which

allow an external device to clock their serial port including most

digital signal processors.

Read Operation

Figure 8 shows a timing diagram for reading from the AD7890

in the Self-Clocking mode. At the end of conversion, RFS goes

low and the serial clock (SCLK) and serial data (DATA OUT)

outputs become active. Sixteen bits of data are transmitted with

one leading zero, followed by the three address bits of the Con-

trol Register, followed by the 12-bit conversion result starting

with the MSB. Serial data is clocked out of the device on the ris-

ing edge of SCLK and is valid on the falling edge of SCLK. The

RFS

output remains low for the duration of the sixteen clock

cycles. On the sixteenth rising edge of SCLK, the RFS output is

driven high and DATA OUT is disabled.

SCLK (O)

DATA OUT (O)

RFS (O)

3-STATE

3-STATE

LEADING

ZERO

DB10

DB0

DB11

A0

A1

A2

t

2

t

3

t

5

t

4

t

6

t

7

t

1

NOTE

(I) SIGNIFIES AN INPUT; (O) SIGNIFIES AN OUTPUT. PULL-UP RESISTOR ON SCLK.

Figure 8. Self-Clocking (Master) Mode Output Register Read