AD9835 datasheet(6/16 Pages) AD

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AD9835

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REV. 0

Table V. Commands

Command

Write 16 Phase bits (Present 8 Bits + 8 Bits

in Defer Register) to Selected PHASE

REG.

Write 8 Phase bits to Defer Register.

Write 16 Frequency bits (Present 8 Bits

+ 8 Bits in Defer Register) to Selected

FREQ REG.

Write 8 Frequency bits to Defer Register.

Bits D9 (PSEL0) and D10 (PSEL1) are

used to Select the PHASE REG when

SELSRC = 1. When SELSRC = 0, the

PHASE REG is selected using the pins

PSEL0 and PSEL1 Respectively.

Bit D11 is used to select the FREQ REG

when SELSRC = 1. When SELSRC = 0,

the FREQ REG is selected using the pin

FSELECT.

This command is used to control the

PSEL0, PSEL1 and FSELECT bits

using only one write. Bits D9 and D10

are used to select the PHASE REG and

Bit 11 is used to select the FREQ REG

when SELSRC = 1. When SELSRC = 0,

the PHASE REG is selected using the

pins PSEL0 and PSEL1 and the FREQ

REG is selected using the pin FSELECT.

Reserved. Configures the AD9835 for

Test Purposes.

Table VI. Controlling the AD9835

D15 D14 Command

Selects source of Control for the PHASE and

FREQ Registers and Enables Synchronization. Bit

D13 is the SYNC Bit. When this bit is High, read-

ing of the FSELECT, PSEL0 and PSEL1 bits/pins

and the loading of the Destination Register with

data is synchronized with the rising edge of MCLK.

The latency is increased by 2 MCLK cycles when

SYNC = 1. When SYNC = 0, the loading of the

data and the sampling of FSELECT/PSEL0/PSEL1

occurs asynchronously. Bit D12 is the Select

Source Bit (SELSRC). When this bit Equals 1, the

PHASE/FREQ REG is Selected using the bits

FSELECT, PSEL0 and PSEL1. When SELSRC =

0, the PHASE/FREQ REG is Selected using the

pins FSELECT, PSEL0 and PSEL1.

Sleep, Reset and Clear. D13 is the SLEEP bit. When

this bit equals 1, the AD9835 is powered down, inter-

nal clocks are disabled and the DAC's current sources

and REFOUT are turned off. When SLEEP = 0, the

AD9835 is powered up. When RESET (D12) = 1,

the phase accumulator is set to zero phase which

corresponds to an analog output of full scale. When

CLR (D11) = 1, SYNC and SELSRC are set to

zero. CLR automatically resets to zero.

Table I. Control Registers

Size

Description

FREQ0 REG

32 Bits

Frequency Register 0. This de-

fines the output frequency, when

FSELECT = 0, as a fraction of the

MCLK frequency.

FREQ1 REG

32 Bits

Frequency Register 1. This de-

fines the output frequency, when

FSELECT = 1, as a fraction of the

MCLK frequency.

PHASE0 REG

12 Bits

Phase Offset Register 0. When

PSEL0 = PSEL1 = 0, the contents

of this register are added to the

output of the phase accumulator.

PHASE1 REG

12 Bits

Phase Offset Register 1. When

PSEL0 = 1 and PSEL1 = 0, the con-

tents of this register are added to the

output of the phase accumulator.

PHASE2 REG

12 Bits

Phase Offset Register 2. When

PSEL0 = 0 and PSEL1 = 1, the

contents of this register are added to

the output of the phase accumulator.

PHASE3 REG

12 Bits

Phase Offset Register 3. When

PSEL0 = PSEL1 = 1, the contents

of this register are added to the

output of the phase accumulator.

Table II. Addressing the Registers

Destination Register

FREG0 REG 8 L LSBs

FREG0 REG 8 H LSBs

FREG0 REG 8 L MSBs

FREG0 REG 8 H MSBs

FREG1 REG 8 L LSBs

FREG1 REG 8 H LSBs

FREG1 REG 8 L MSBs

FREG1 REG 8 H MSBs

PHASE0 REG 8 LSBs

PHASE0 REG 8 MSBs

PHASE1 REG 8 LSBs

PHASE1 REG 8 MSBs

PHASE2 REG 8 LSBs

PHASE2 REG 8 MSBs

PHASE3 REG 8 LSBs

PHASE3 REG 8 MSBs

Table III. 32-Bit Frequency Word

Table IV. 12-Bit Frequency Word

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