AD9835

–13–

REV. 0

APPLICATIONS

The AD9835 contains functions that make it suitable for

modulation applications. The part can be used to perform

simple modulation such as FSK. More complex modulation

schemes such as GMSK and QPSK can also be implemented

using the AD9835. In an FSK application, the two frequency

registers of the AD9835 are loaded with different values; one

frequency will represent the space frequency while the other will

represent the mark frequency. The digital data stream is fed to

the FSELECT pin, which will cause the AD9835 to modulate

the carrier frequency between the two values.

The AD9835 has four phase registers; this enables the part to

perform PSK. With phase shift keying, the carrier frequency is

phase shifted, the phase being altered by an amount that is

related to the bit stream being input to the modulator. The

presence of four shift registers eases the interaction needed

between the DSP and the AD9835.

The AD9835 is also suitable for signal generator applications.

With its low current consumption, the part is suitable for

applications in which it can be used as a local oscillator.

Grounding and Layout

The printed circuit board that houses the AD9835 should be

designed so that the analog and digital sections are separated

and confined to certain areas of the board. This facilitates the

use of ground planes which can be separated easily. A minimum

etch technique is generally best for ground planes as it gives the

best shielding. Digital and analog ground planes should only be

joined in one place. If the AD9835 is the only device requiring

an AGND to DGND connection, then the ground planes

should be connected at the AGND and DGND pins of the

AD9835. If the AD9835 is in a system where multiple devices

require AGND to DGND connections, the connection should

be made at one point only, a star ground point that should be

established as close as possible to the AD9835.

Avoid running digital lines under the device as these will couple

noise onto the die. The analog ground plane should be allowed

to run under the AD9835 to avoid noise coupling. The power

supply lines to the AD9835 should use as large a track as is

possible to provide low impedance paths and reduce the effects

of glitches on the power supply line. Fast switching signals

such as clocks should be shielded with digital ground to avoid

radiating noise to other sections of the board. Avoid crossover

of digital and analog signals. Traces on opposite sides of the

board should run at right angles to each other. This will reduce

the effects of feedthrough through the board. A microstrip

technique is by far the best but is not always possible with a

double-sided board. In this technique, the component side of

the board is dedicated to ground planes while signals are placed

on the other side.

Good decoupling is important. The analog and digital supplies

to the AD9835 are independent and separately pinned out to

minimize coupling between analog and digital sections of the

device. All analog and digital supplies should be decoupled to

AGND and DGND respectively with 0.1

µF ceramic capacitors

in parallel with 10

µF tantalum capacitors. To achieve the best

from the decoupling capacitors, they should be placed as close

as possible to the device, ideally right up against the device. In

systems where a common supply is used to drive both the

AVDD and DVDD of the AD9835, it is recommended that the

system’s AVDD supply be used. This supply should have the

recommended analog supply decoupling between the AVDD

pins of the AD9835 and AGND and the recommended digital

supply decoupling capacitors between the DVDD pins and

DGND.

Interfacing the AD9835 to Microprocessors

The AD9835 has a standard serial interface that allows the part

to interface directly with several microprocessors. The device

uses an external serial clock to write the data/control informa-

tion into the device. The serial clock can have a frequency of

20 MHz maximum. The serial clock can be continuous or it

can idle high or low between write operations. When data/

control information is being written to the AD9835, FSYNC

is taken low and held low while the 16 bits of data are being

written into the AD9835. The FSYNC signal frames the 16 bits

of information being loaded into the AD9835.

AD9835-to-ADSP-21xx Interface

Figure 24 shows the serial interface between the AD9835 and

the ADSP-21xx. The ADSP-21xx should be set up to operate

in the SPORT Transmit Alternate Framing Mode (TFSW = 1).

The ADSP-21xx is programmed through the SPORT control

register and should be configured as follows: Internal clock

operation (ISCLK = 1), Active low framing (INVTFS = 1),

16-bit word length (SLEN = 15), Internal frame sync signal

(ITFS = 1), Generate a frame sync for each write operation

(TFSR = 1). Transmission is initiated by writing a word to the

Tx register after the SPORT has been enabled. The data is

clocked out on each rising edge of the serial clock and clocked

into the AD9835 on the SCLK falling edge.

ADSP-2101/

ADSP-2103

AD9835

TFS

DT

SCLK

FSYNC

ADDITIONAL PINS OMITTED FOR CLARITY

SDATA

SCLK

Figure 24. ADSP-2101/ADSP-2103-to-AD9835 Interface

AD9835-to-68HC11/68L11 Interface

Figure 25 shows the serial interface between the AD9835 and

the 68HC11/68L11 microcontroller. The microcontroller is

configured as the master by setting bit MSTR in the SPCR to 1

and, this provides a serial clock on SCK while the MOSI output

drives the serial data line SDATA. Since the microcontroller

does not have a dedicated frame sync pin, the FSYNC signal is

derived from a port line (PC7). The setup conditions for cor-

rect operation of the interface are as follows: the SCK idles high

between write operations (CPOL = 0), data is valid on the SCK

falling edge (CPHA = 1). When data is being transmitted to the

AD9835, the FSYNC line is taken low (PC7). Serial data from

the 68HC11/68L11 is transmitted in 8-bit bytes with only eight