AD9835 datasheet(2/16 Pages) AD

2 / 16 page

–2–

REV. 0

AD9835–SPECIFICATIONS1

(VDD = +5 V

5%; AGND = DGND = 0 V; TA = TMIN to TMAX; REFIN = REFOUT;

RSET = 3.9 k ; RLOAD = 300

for IOUT, unless otherwise noted)

Parameter

AD9835B

Units

Test Conditions/Comments

SIGNAL DAC SPECIFICATIONS

Resolution

Bits

Update Rate (fMAX)

MSPS nom

IOUT Full Scale

mA nom

4.75

mA max

Output Compliance

1.35

V max

DC Accuracy

Integral Nonlinearity

±1

LSB typ

Differential Nonlinearity

±0.5

LSB typ

DDS SPECIFICATIONS2

Dynamic Specifications

Signal-to-Noise Ratio

dB min

fMCLK = 50 MHz, fOUT = 1 MHz

Total Harmonic Distortion

–52

dBc max

fMCLK = 50 MHz, fOUT = 1 MHz

Spurious Free Dynamic Range (SFDR)3

fMCLK = 6.25 MHz, fOUT = 2.11 MHz

Narrow Band (

±50 kHz)

–72

dBc min

Wide Band (

±2 MHz)

–50

dBc min

Clock Feedthrough

–60

dBc typ

Wake-Up Time

ms typ

Power-Down Option

Yes

VOLTAGE REFERENCE

Internal Reference @ +25

°C

1.21

V typ

TMIN to TMAX

1.21

± 7%

V min/max

REFIN Input Impedance

Ω typ

Reference TC

100

ppm/

°C typ

REFOUT Output Impedance

300

Ω typ

LOGIC INPUTS

VINH, Input High Voltage

DVDD – 0.9

V min

VINL, Input Low Voltage

0.9

V max

IINH, Input Current

µA max

CIN, Input Capacitance

pF max

POWER SUPPLIES

fMCLK = 50 MHz

AVDD

4.75/5.25

V min/V max

DVDD

4.75/5.25

V min/V max

IAA

5mA max

IDD

2.5 + 0.33/MHz

mA typ

IAA + IDD

mA max

Low Power Sleep Mode

0.35

mA max

NOTES

1Operating temperature range is as follows: B Version: –40

°C to +85°C.

2100% production tested.

MCLK = 6.25 MHz, Frequency Word = 5671C71C HEX, f OUT = 2.11 MHz.

4Measured with the digital inputs static and equal to 0 V or DVDD. The AD9835 is tested with a capacitive load of 50 pF. The part can be operated with higher

capacitive loads, but the magnitude of the analog output will be attenuated. See Figure 5.

Specifications subject to change without notice.

IOUT

COMP

REFIN

ADJUST

REFOUT

AD9835

ON-BOARD

REFERENCE

10-BIT

DAC

COS

ROM

FULL-SCALE

CONTROL

300

50pF

RSET

3.9k

10nF

AVDD

Figure 1. Test Circuit with Which Specifications Are Tested

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