ADMC330 datasheet(6/20 Pages) AD

6 / 20 page

ADMC330

–6–

REV. 0

four configuration registers (PWMTM, PWMDT, PWMPD

and PWMGATE), which define basic waveform parameters

such as the master switching frequency, deadtime, minimum

pulsewidth, and gate drive chopping. There PWM output sig-

nals on the pins AH through CL are controlled by the input

registers (PWMCHA, PWMCHB, PWMCHC and PWMSEG)

and the control pins

PWMTRIP and PWMPOL.

PWM Controller Overview

The PWM controller consists of three units: the center-based

timing unit, output control unit and the gate drive unit as shown

in Figure 1.

• The center-based PWM timing unit is the core of the PWM

controller and produces three pairs of complemented and

deadtime adjusted PWM waveforms as required for ac motor

control.

• The output control unit is a signal switching unit that selects

the appropriate PWM signals to be connected to the output

pins based on the bits set in the segment register (PWMSEG)

as may be required for ECM control or some space vector

modulation schemes.

• The gate drive block sets the logic polarity of the PWM “on”

signal according to the polarity of the PWMPOL pin to match

the gate drive circuit requirement. It can also modulate the

PWM “on” signal with a high frequency carrier (0.08 MHz–

5 MHz) if required for a transformer coupled gate drive circuit.

The DSP-based control algorithm can be synchronized to the

PWM generator by a hardware interrupt signal that is generated

at the end of every PWM switching cycle. This same PWMSYNC

signal is internally connected to the internal analog-to-digital

converter and is also available at an output pin. Finally, the

hardware

PWMTRIP pin can be used to shut down the PWM

controller in the event of a fault.

Center-Based PWM Timing Unit

The center-based PWM timing unit is a programmable timer

that generates three pairs of fixed frequency PWM waveforms

suitable for controlling a three-phase power inverter. The unit

contains arithmetic circuits that calculate the PWM signal tim-

ing edges from waveform parameters such as the PWM period,

CENTER-BASED

PWM TIMING

UNIT

PWMTM

PWMCHA

PWMDT

PWMCHB

PWMCHC

CLK

SYNC

RESET

HCLK

PWMSYNC

INTERRUPT

SIGNALS

TIMING CONTROL

REGISTERS

CHANNEL

REGISTERS

OUTPUT

CONTROL

UNIT

SYNC

PWMSEG

OUTPUT CONTROL

PWMGATE

GATE CONTROL

GATE

DRIVE

UNIT

CLK

PWMPOL

PWMTRIP

PWMSYNC

PWMPD

GATE CONTROL

Figure 1. PWM Controller Overview

dead time and the duty cycle for each inverter phase. There is

no extra DSP software overhead once the duty cycle for each

phase has been calculated and loaded into the PWM channel

registers.

The PWM Timing Unit produces three pairs of complemented

variable duty cycle waveforms symmetrical about common axes

of the form shown in Figure 2. They are complemented wave-

forms, which means that for any pair of PWM waveforms (AH

and AL), they can never both be ON at the same time. They are

deadtime adjusted, which means that for any pair of PWM

waveforms, there is a delay between switching from being ON in

one waveform to being ON in the complemented waveform. A

pulse deletion function is implemented, which means that very

narrow PWM pulses will not be generated.

It is important to note that the deadtime compensation does not

take place on the boundary between consecutive PWM cycles.

Thus both the low side and high side devices can switch on

during the transition from a full-ON state to any other state.

This potentially volatile condition can be avoided by:

• Ensuring that the device never enters to the full-ON or full-

OFF states, that is,

PWMCHx

≤ PWMTM –2 × (PWMDT + 1), with PWMPD = 0

• Using an external deadtime compensation circuit.

There is an active high PWMSYNC pulse produced at the be-

ginning of each PWM cycle to synchronize the operation of

other peripherals with the switching of the power inverter. This

signal is also internally connected to the ADC block to initiate

conversions, and to the DSP core to generate an interrupt.

Figure 2 shows the center-based PWM operation.

The master switching frequency can range from 2.5 kHz to

25 kHz and is an integral fraction of HCLK clock frequency. It

is set by the value in the 12-bit PWMTM period register, which

sets the total number of clock cycles in a PWM cycle. The

required PWM period as a function of the desired master

switching frequency (fPWM) and peripheral system clock fre-

quency (fHCLK) is given by:

PWMTM

f HCLK

f PWM

ADMC330 Datasheet(PDF) 6 Page - Analog Devices

ADMC330 Datasheet(HTML) 6 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

Datasheet Download

Link URL