ADMC330 datasheet(14/20 Pages) AD

14 / 20 page

ADMC330

–14–

REV. 0

The interrupt control register, ICNTL, allows the external inter-

rupts to be either edge- or level-sensitive. Since the

IRQ2 line is

a combination of all peripheral interrupt sources, they will all be

set to edge- or level-sensitive. Level-sensitive is recommended

when using both PIO and PWM interrupts together. When

simultaneous PIO and PWM interrupts occur, the

IRQ2 line is

brought low and held low until both the PIO and PWM inter-

rupts are acknowledged. If interrupts are set to edge-sensitive

only, one

IRQ2 interrupt will occur for simultaneous interrupts

and it is incumbent on the interrupt service routine to check for

simultaneous interrupts. If, however, interrupts are set to level-

sensitive, all simultaneous interrupts are detected because

IRQ2

is held low until all interrupts are acknowledged.

The ICNTL register also allows interrupts to be sequentially

processed or nested with higher priority interrupts taking prece-

dence. Since the peripheral interrupts are all on the same level

(

IRQ2), they can only be nested by manually unmasking them

with the IMASK register from inside the interrupt service routine.

The IFC register is a write-only register, which is used to force

and clear interrupts from software.

On-chip stacks preserve the processor status and are automati-

cally maintained during interrupt handling. The stacks are 12

levels deep to allow interrupt nesting. A set of shadow registers

are provided for single context switching.

Power-Down

The ADMC330 can be put in a lower power state from software

control by setting the PDFORCE bit in the SPORT1 Autobuffer/

Power-Down register. This causes a power-down interrupt;

execution then continues at the power-down interrupt vector

location 0x002C. The power-down interrupt vector location is

shared with the

PWMTRIP interrupt, thus if a different inter-

rupt service routine is required, the vector must be changed

prior to setting the PDFORCE bit. The power-down interrupt

service routine must perform a peripheral reset prior to entering

power-down to shut down the PWM signals to the motor. The

interrupt service routine can then perform any housekeeping

operations prior to executing an IDLE instruction, after which

the ADMC330 is in power-down mode. The only way out of

power-down is to perform a hardware reset of the ADMC330.

Clock Signals

The ADMC330 can be clocked by either a crystal or a TTL-

compatible clock signal.

The CLKIN input cannot be halted, changed during operation

or operated below the specified frequency during normal operation.

If an external clock is used, it should be a TTL-compatible

signal running at half the instruction rate. The signal is con-

nected to the processor’s CLKIN input. When an external clock

is used, the XTAL input must be left unconnected.

The ADMC330 uses an input clock with a frequency equal to

half the instruction rate; a 10 MHz input clock yields a 50 ns

processor cycle (which is equivalent to 20 MHz). Normally,

instructions are executed in a single processor cycle. All device

timing is relative to the internal instruction clock rate, which is

indicated by the CLKOUT signal when enabled.

Because the ADMC330 includes an on-chip oscillator circuit,

an external crystal may be used. The crystal should be con-

nected across the CLKIN and XTAL pins, with two capacitors

connected as shown in Figure 10. A parallel-resonant, funda-

mental frequency, microprocessor-grade crystal should be used.

10M

CLKIN

XTAL

Figure 10. External Crystal Connections

A clock output (CLKOUT) signal is generated by the processor

at the processor’s cycle rate.

Reset

The

RESET signal initiates a master reset of the ADMC330.

The

RESET signal must be asserted during the power-up se-

quence to assure proper initialization.

RESET during initial

power-up must be held long enough to allow the internal clock

to stabilize. If

RESET is activated any time after power-up, the

clock continues to run and does not require stabilization time.

The power-up sequence is defined as the total time required for

the crystal oscillator circuit to stabilize after a valid VDD is ap-

plied to the processor, and for the internal phase-locked loop

(PLL) to lock onto the specific crystal frequency. A minimum of

2000 CLKIN cycles ensures that the PLL has locked, but does

not include the crystal oscillator start-up time. During this

power-up sequence the

RESET signal should be held low.

The

RESET input contains some hysteresis; however, if you

use an RC circuit to generate your

RESET signal, the use of an

external Schmitt trigger is recommended.

The master reset sets all internal stack pointers to the empty

stack condition, masks all interrupts and clears the MSTAT

RESET is released, the DSP starts running from

the internal ROM and the boot loading sequence is performed.

If an SROM (serial ROM) or Serial EEPROM is connected to

SPORT1 with valid program data, this code is then loaded and

execution starts. If a valid device is not detected, then the pro-

gram defaults to debug mode with SPORT1 configured as a

UART running at 9600 baud.

ADMC330 Datasheet(PDF) 14 Page - Analog Devices

ADMC330 Datasheet(HTML) 14 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

Datasheet Download

Link URL