ADMC330 datasheet(9/20 Pages) AD

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ADMC330

–9–

REV. 0

PWMGATE

GATETM

GATE DRIVE CHOPPING FREQUENCY

(fHCLK) /(2(GATETM+1))

LOW SIDE GATE CHOPPING

HIGH SIDE GATE CHOPPING

1 = ENABLE

0 = DISABLE

A CHANNEL CROSSOVER

B CHANNEL CROSSOVER

CH OUTPUT DISABLE

CL OUTPUT DISABLE

BH OUTPUT DISABLE

BL OUTPUT DISABLE

AH OUTPUT DISABLE

AL OUTPUT DISABLE

1 = DISABLE

0 = ENABLE

1 = CROSSOVER

0 = NO CROSSOVER

PWMSEG

C CHANNEL CROSSOVER

Figure 4. Configuration of PWMSEG and PWMGATE Registers

Table I. ADC Auxiliary Channel Selection

MODECTRL (1)

MODECTRL (0)

Select

ADCMUX1

ADCMUX0

VAUX0

VAUX1

VAUX2

VAUX3

Analog Block

The operation of the ADC block may be explained by reference

to Figures 5 and 6. The reference ramp is tied to one input of

each of the four comparators. This reference ramp is generated

by charging an external timing capacitor with a constant current

source. The timing capacitor is connected between pins CAPIN

and SGND. The capacitor voltage is reset at the start of each

PWM cycle using the PWMSYNC pulse, which is held high for

20 CLKIN cycles (TCRST = 2

µs for a 10 MHz CLKIN). On the

falling edge of PWMSYNC, the capacitor begins to charge at a

rate determined by the capacitor and the current source values.

An internal current source is made available for connection to

the external timing capacitor on the ICONST pin. An external

current source could also be used, if required. The four input

comparators of the ADC block continuously compare the values

of the four analog inputs with the capacitor voltage. Each com-

parator output will go high when the capacitor voltage exceeds

the respective analog input voltage.

ADC Timer Block

The ADC timer block consists of a 12-bit counter clocked at a

constant rate of HCLK, equal to half the DSP clock rate. This

gives a timer resolution of 100 ns at the maximum CLKIN

frequency of 10 MHz. The counter is reset on the falling edge of

the PWMSYNC pulse so that the counter commences at the

beginning of the reference voltage ramp. When the output of a

given comparator goes high, the counter value is latched into the

appropriate 12-bit ADC register. There are four ADC registers

(ADC1, ADC2, ADC3 and ADCAUX) corresponding to each

of the four comparators. At the end of the reference voltage

ramp, all four registers should have been loaded with new values

so that new conversion data is available to the controller after a

PWMSYNC interrupt.

The first set of values loaded into the output registers after the

first PWMSYNC interrupt will be invalid since the latched value

is indeterminate. For very low analog inputs, less than the mini-

mum reference value, the comparator output will be perma-

nently high and the output register will contain the code 0x000.

Also, if the input analog voltage exceeds the peak capacitor

ramp voltage, the comparator output will be permanently low

and a 0xFFF code will be produced. This indicates an input

overvoltage condition.

REFOUT

ICONST

CAPIN

SGND

VAUX0

VAUX1

VAUX2

VAUX3

ADC

TIMER

BLOCK

ADC1

ADC2

ADC3

ADCAUX

ADMUX0

ADMUX1

4-1

MUX

PWMSYNC

ADC REGISTERS

HCLK

ADC1

ADC3

Figure 5. ADC Overview

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