ADMC330 datasheet(11/20 Pages) AD

11 / 20 page

ADMC330

–11–

REV. 0

PIODIR

PIODATA

(READ/WRITE)

PIOFLAG

(READ-ONLY)

PIOINTEN

(WRITE-ONLY)

1 = OUTPUT

0 = INPUT

1 = OUTPUT

0 = INPUT

1 = HI

0 = LOW

1 = ENABLE INTERRUPT

0 = DISABLE INTERRUPT

1 = INTERRUPT FLAGGED

0 = NO INTERRUPT

PIO0

PIO7

Figure 8. Configuration of PIO Registers

R1 = R2 = 13k

C1 = C2 = 10nF

PWMDAC

Figure 7. Auxiliary PWM Output Filter

PROGRAMMABLE DIGITAL INPUT/OUTPUT

The ADMC330 has eight programmable digital I/O (PIO) pins:

PIO0–PIO7. Each pin can be individually configurable as either

an input or an output. Input pins can also be used to generate

interrupts.

The PIO pins are configured as input or output by setting the

appropriate bits in the PIODIR register, as shown in Figure 8.

The read/write register PIODATA is used to set the state of an

output pin or read the state of an input pin. Writing to PIODATA

affects only the pins configured as outputs. The default state,

after an ADMC330 reset, is that all PIO are configured as inputs.

Any pin can be configured as an independent edge triggered

interrupt source. The pin must first be configured as an input

and then the appropriate bit must be set in the PIOINTEN

changes on any PIO pin configured as an interrupt source. A

PIO interrupt sets the appropriate bit in the PIOFLAG register.

The DSP peripheral interrupt service routine (ISR) must read

the PIOFLAG registers to determine which PIO pin was the

source of the PIO interrupt. Reading the PIOFLAG register will

clear it.

WATCHDOG TIMER OVERVIEW

The watchdog timer can be used to reset the DSP and peripher-

als in the event of a software error hanging the processor. The

watchdog timer is enabled by writing a value to the watchdog

timer register. In the event of the code “hanging” the counter

will count down from its initial value to zero and the watchdog

timer hardware will force a DSP and peripheral reset. In normal

operation a section of DSP code will write to the timer register

to reset the counter to its initial value preventing it from reach-

ing zero.

DSP CORE ARCHITECTURE OVERVIEW

Figure 9 is a block diagram of the ADMC330 processor core

and system peripherals. The processor contains three indepen-

dent computational units: The ALU, the multiplier/accumulator

(MAC) and the shifter. The computational units process 16-bit

data directly and have provisions to support multiprecision

computations. The ALU performs a standard set of arithmetic

and logic operations; division primitives are also supported. The

MAC performs single-cycle multiply, multiply/add and multiply/

subtract operations with 40 bits of accumulation. The shifter

performs logical and arithmetic shifts, normalization, denormali-

zation and derive exponent operations. The shifter can be used to

efficiently implement numeric format control including multi-

word and block floating-point representations.

The internal result (R) bus directly connects the computational

units so that the output of any unit may be the input of any unit

on the next cycle.

ADMC330 Datasheet(PDF) 11 Page - Analog Devices

ADMC330 Datasheet(HTML) 11 Page - Analog Devices

Html Pages

1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20

Datasheet Download

Link URL