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ADMC330

–7–

REV. 0

PWMDT

START

END

PWMDT

PWMSYNC

PWMDT

PWMCHC

PWMCHB

PWMTM

PWMCHA

Figure 2. Three-Phase Center-Based Active Low PWM Waveforms

For example, the HCLK clock is 10 MHz. If 8 kHz PWM

waveforms are required, then PWMTM should be loaded

with 10 MHz/8 kHz = 1250. A value must be written to the

PWMTM register before the PWM block can be used.

The ON time of each pair of PWM waveforms, e.g., AH and AL,

is set by the integer value in the duty cycle registers PWMCHA,

PWMCHB and PWMCHC. The deadtime between the active

portions of complementary waveforms is set by the value in the

deadtime register PWMDT and is subtracted from the value in

the duty cycle register. The final deadtime adjusted fractional

duty cycle for Channel A for example is given by:

dA =

tAon

T PWM

PWMCHA – PWMDT

PWMTM

The minimum pulsewidth delivered is set by the value in the

pulse deletion register PWMPD. When the calculated high or

low pulsewidth for any channel is less than PWMPD, the

switching pulse is eliminated and the outputs are saturated one

to 100% high, and the other to 100% low.

Output Control Unit

The Output Control Unit contains special features that allow

the ADMC330 to be easily applied for the control of electroni-

cally commutated motors (ECM) or brushless dc motors

(BDCM). In these machines, only two motor phases are required

to conduct simultaneously so that at most two power switches are

turned on at any time. In order to build up current in the motor

phases, it is necessary to turn on the upper switch in one phase and

the lower switch in another phase of the inverter.

The PWMSEG register of the ADMC330 PWM block allows

modification of the pulsewidth modulation signals from the

center-based block in order to meet the requirements for ECM

control. Three bits of the PWMSEG register (Bits 6, 7 and 8)

permit individual crossover of the three PWM signal pairs. For

example, setting Bit 8 will crossover the signals for Phase A such

that the high-side signal from the center-based block will ulti-

mately appear at the low-side output pin (AL). Conversely, the

low-side signal from the center-based block will appear at Pin AH.

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