ADMC330 datasheet(13/20 Pages) AD

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ADMC330

–13–

REV. 0

Serial Ports

The ADMC330 incorporates two complete synchronous serial

ports (SPORT0 and SPORT1) for serial communications and

multiprocessor communication.

Following is a brief list of the capabilities of the ADMC330

SPORTs. Refer to the ADSP-2100 Family User’s Manual for

further details.

• SPORTs are bidirectional and have a separate, double-buff-

ered transmit and receive section.

• SPORTs can use an external serial clock or generate their

own serial clock internally.

• SPORTs have independent framing for the receive and trans-

mit sections. Sections run in a frameless mode or with frame

synchronization signals internally or externally generated.

Frame sync signals are active high or inverted, with either of

two pulsewidths and timings.

• SPORTs support serial data word lengths from 3 to 16 bits

and provide optional A-law and

µ-law companding according

to CCITT recommendation G.711.

• SPORT receive and transmit sections can generate unique

interrupts on completing a data word transfer.

• SPORTs can receive and transmit an entire circular buffer of

data with only one overhead cycle per data word. An interrupt

is generated after a data buffer transfer.

• SPORT0 has a multichannel interface to selectively receive

and transmit a 24- or 32-word, time-division multiplexed,

serial bit stream.

• SPORT1 can be configured to have two external interrupts

(

IRQ0 and IRQ1) and the Flag In and Flag Out signals. The

internally generated serial clock may still be used in this

configuration.

• SPORT1 has two multiplexed data receive pins DR1A and

DR1B. DR1A is automatically selected at boot up and is the

default input for the serial ROM. For UART communication

DR1B is selected.

A full description of the SPORT timing parameters is given in

Figure 14.

Interrupts

The interrupt controller allows the processor core to respond to

nine possible interrupts with the minimum of overhead. The

ADMC330 supports eight internal interrupts from the timer,

the two serial ports, the software interrupts, and the software

forced power-down interrupt. The ninth interrupt,

IRQ2 on the

2171 core, is actually wired internally to the ADMC330 periph-

eral interrupt sources. This peripheral interrupt is generated on

a PWM trip, PWMSYNC (once each PWM cycle), or from any

of the eight PIO ports. The PWMSYNC interrupt is triggered

by a low to high transition on the PWMSYNC pulse.

The

PWMTRIP interrupt is triggered on a high-to-low transi-

tion on the

PWMTRIP pin. A PIO interrupt is detected on any

change of state (high-to-low or low-to-high) on the PIO line.

When a peripheral interrupt is detected, a flag bit is set in the

IRQFLAG register for PWMSYNC and

PWMTRIP or in the

PIOFLAG register for a PIO interrupt, and the

IRQ2 line is

pulled low. The

IRQ2 line is held low until all pending periph-

eral interrupts are acknowledged. Execution then begins at the

IRQ2 (or peripheral) interrupt vector location (0x004). Soft-

ware at this location further determines if the source of the

interrupt was a PWM trip, PWYMSYNC, or PIO, by reading

the IRQFLAG register, and vectors to the appropriate interrupt

vector location. If more than one interrupt occurs simultaneously,

the higher priority interrupt service routine is executed. The

software at location 0x004 is provided in a default interrupt

vector table that is created by the on-chip boot ROM code.

Therefore, a user need only put the interrupt service routine

for the given interrupt at the interrupt vector location shown in

Table IV. Reading the IRQFLAG register clears the

PWMTRIP

and PWMSYNC bits and acknowledges the interrupt, thus

allowing further interrupts when the interrupt service routine

exits. When the IRQFLAG register is read, it is saved in a data

memory variable so the user interrupt service routines can check

to see if there were simultaneous

PWMTRIP and PWMSYNC

interrupts.

A user’s PIO interrupt service routine must read the PIOFLAG

rupt. Reading the PIOFLAG register clears all bits in the

interrupts when the interrupt service routine exits.

All interrupts are internally prioritized and individually maskable

(except for power-down). The interrupt vector locations and

priorities for all interrupts are listed in Table IV. Interrupts can

be masked or unmasked with the IMASK register. Individual

interrupt requests are logically ANDed with the bits in IMASK;

the higher priority unmasked interrupt is then selected. The

software forced power-down interrupt is nonmaskable. The

ADMC330 masks all interrupts for one instruction cycle follow-

ing the execution of an instruction that modifies the IMASK

Table IV. Interrupt Priority and Interrupt Vector Addresses

Interrupt

Source of Interrupt

Vector Location (Hex)

Reset

0x0000 (Reserved)

PWMTRIP and Power-Down*

0x002C (Highest Priority)

PWMSYNC*

0x000C

PIO*

0x0008

SPORT0 Transmit

0x0010

SPORT0 Receive

0x0014

Software Interrupt 1

0x0018

Software Interrupt 0

0x001C

SPORT1 Transmit or

IRQ1

0x0020

SPORT1 Receive or

IRQ0

0x0024

Timer

0x0028 (Lowest Priority)

*Peripheral interrupt (

IRQ2) starts execution at 0x004, software further vector

to 0x002C, 0x000C or 0x0008 as appropriate.

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