REV. A

ADP3155

–6–

SD

DRIVE1

SENSE+

SENSE–

DRIVE2

PGND

AGND

CMP

12V

1k

1 F

4700pF

0.1 F

1.2V

100k

0.1 F

ADP3155

OP27

VID0–

VID4

5-BIT CODE

Figure 13. Closed-Loop Test Circuit for Accuracy

THEORY OF OPERATION

The ADP3155 uses a current-mode, constant-off-time control

technique to switch a pair of external N-channel MOSFETs in

a synchronous buck topology. Constant off-time operation

offers several performance advantages, including that no slope

compensation is required for stable operation. A unique feature

of the constant-off-time control technique is that since the off-

time is fixed, the converter’s switching frequency is a function

of the ratio of input voltage to output voltage. The fixed off-

time is programmed by the value of an external capacitor con-

regulated output voltage is maintained as described below in the

cycle-by-cycle operation. Under fixed operating conditions the

on-time does not vary, and it varies only slightly as a function of

load. This means that switching frequency is fairly constant in

standard VRM applications. In order to maintain a ripple cur-

rent in the inductor that is independent of the output voltage

(which also helps control losses and simplify the inductor de-

sign), the off-time is made proportional to the value of the out-

put voltage. Normally, the output voltage is constant and,

therefore, the off-time is constant as well.

Active Voltage Positioning

The output voltage is sensed at the SENSE– pin. A voltage-

voltage and a programmable reference voltage. The reference

voltage is programmed to between 1.3 V and 3.5 V by an inter-

nal 5-bit DAC, which reads the code at the voltage identifica-

tion (VID) pins. (Refer to Table I for output voltage vs. VID pin

code information.) A unique supplemental regulation technique

called active voltage positioning with optimal compensation

adjusts the output voltage as a function of the load current so

that it is always optimally positioned for a load transient. Stan-

dard (passive) voltage positioning, sometimes recommended for

use with other architectures, has poor dynamic performance

which renders it ineffective under the stringent repetitive tran-

sient conditions specified in Intel VRM documents. Conse-

quently, such techniques do not allow the minimum possible

number of output capacitors to be used. Optimally compen-

sated active voltage positioning as used in the ADP3155 pro-

vides a bandwidth for transient response that is limited only by

parasitic output inductance. This yields optimal load transient

response with the minimum number of output capacitors.

Table I. Output Voltage vs. VID Code

VID4

VID3

VID2

VID1

VID0

011111.30

011101.35

011011.40

011001.45

010111.50

010101.55

010011.60

010001.65

001111.70

001101.75

001011.80

001001.85

000111.90

000101.95

000012.00

000002.05

11111No CPU–Shutdown

111102.10

111012.20

111002.30

110112.40

110102.50

110012.60

110002.70

101112.80

101102.90

101013.00

101003.10

100113.20

100103.30

100013.40

100003.50

Cycle-by-Cycle Operation

During normal operation (when the output voltage is regulated),

the voltage-error amplifier and the current comparator (CMPI)

are the main control elements. (See the block diagram of Figure

3.) During the on-time of the high side MOSFET, CMPI moni-

tors the voltage between the SENSE+ and SENSE– pins. When

the voltage level between the two pins reaches the threshold level

then discharged at a rate determined by the off-time controller.

While the timing capacitor is discharging, the low side drive

output goes high, turning on the low side MOSFET. When the

voltage level on the timing capacitor has discharged to the thresh-

The output of the flip-flop forces the low side drive output to go

low and the high side drive output to go high. As a result, the low

side switch is turned off and the high side switch is turned on.

The sequence is then repeated. As the load current increases, the

output voltage starts to decrease. This causes an increase in the

output of the voltage-error amplifier, which, in turn, leads to an

the load current. To prevent cross conduction of the external

MOSFETs, feedback is incorporated to sense the state of the driver

output pins. Before the low side drive output can go high, the

high side drive output must be low. Likewise, the high side drive

output is unable to go high while the low side drive output is high.