REV. A

ADP3155

–10–

high side FET, however, is turned on with only 12 V – 5 V = 7 V.

Checking the typical output characteristics of the device in the

data sheet shows that for an output current of 10 A, and at a

crease due to the reduced gate drive can be neglected. The

ture of +140

°C must be modified by an R

using the graph in the data sheet. In this case:

14 m

Ω = 24 mΩ.

The high side FET dissipation is:

where the second term represents the turn-off loss of the FET.

provided by the ADP3155 is about 1 A.)

The low side FET dissipation is:

(Note that there are no switching losses in the low side FET.)

To maintain an acceptable MOSFET junction temperature,

proper heat sinks should be used. The Thermalloy 6030 heat

sink has a thermal impedance of 13

°C/W with convection cool-

ing. With this heat sink, the junction-to-ambient thermal imped-

ance of the chosen high side FET

θ

sink-to-ambient) + 2

°C/W (junction-to-case) + 0.5°C/W (case-

to-heat sink) = 15.5

°C/W.

At full load, and at +50

°C ambient temperature, the junction

temperature of the high side FET is:

The same heat sink may be used for the low side FET, e.g., the

Thermalloy type 7141 (

θ = 20.3°C/W). With this heat sink, the

junction temperature of the low side FET is:

All of the above-calculated junction temperatures are safely

below the +175

°C maximum specified junction temperature of

the selected FETs.

The maximum operating junction temperature of the ADP3155

is calculated as follows:

where

θ

is equal to 110

°C/W and I

follows:

The result is:

In continuous inductor-current mode, the source current of the

capacitors with low equivalent series resistance (ESR) and ad-

equate ripple-current rating must be connected across the input

terminals. The maximum rms current of the input bypass

capacitors is:

For an FA-type capacitor with 2700

µF capacitance and

10 V voltage rating, the ESR is 34 m

Ω and the allowed ripple

current at 100 kHz is 1.94 A. At +105

°C, at least four such

capacitors must be connected in parallel to handle the calculated

ripple current. At +50

°C ambient, however, a higher ripple

current can be tolerated, so three capacitors in parallel are

adequate.

The ripple voltage across the three paralleled capacitors is:

140 mV p-p

To further reduce the effect of the ripple voltage on the system

supply voltage bus and to reduce the input-current di/dt to

below the recommended maximum of 0.1 A/

µs, an additional

small inductor (L > 1.7

µH @ 10 A) should be inserted between

the converter and the supply bus (see Figure 2).

Feedback Loop Compensation Design for Active Voltage

Positioning

Optimized compensation of the ADP3155 allows the best pos-

sible containment of the peak-to-peak output voltage deviation.

Any practical switching power converter is inherently limited by

the inductor in its output current slew rate to a value much less

than the slew rate of the load. Therefore, any sudden change of

load current will initially flow through the output capacitors,

and this will produce an output voltage deviation equal to the

ESR of the output capacitor array times the load current change.

To correctly implement active voltage positioning, the low fre-

quency output impedance (i.e., the output resistance) of the

converter should be made equal to the maximum ESR of the

output capacitor array. This can be achieved by having a single

the pole frequency coincides with the ESR zero of the output

amplifier output pin be terminated by the parallel combination

of a resistor and capacitor. The required resistor value can be

calculated from the equation:

R

kRt

kRt

C

TOTAL

TOTAL

=

×

275

275

Ω

Ω –

where:

Rt

kR

I

VV

TOTAL

CS

OMAX

HI

LO

=

××

16 4

.

–

Ω

and where the quantities 16.4 k

Ω and 275 kΩ are characteristic

has already been determined as above.

the proper voltage positioning gain, the dc biasing of that resis-

tor would determine how the regulation band is centered (i.e.,

offset). Note that sometimes the specified regulation band is

asymmetrical with respect to the nominal VID voltage. With the

ADP3155, the offset is already considered part of the design

procedure—no special provision is required. To accomplish the