REV. A

ADP3155

–7–

Power Good

The ADP3155 has an internal monitor that senses the output

voltage and drives the PWRGD pin of the device. This pin is an

open drain output whose high level (when connected to a pull-

up resistor) indicates that the output voltage has been within a

±5% regulation band of the targeted value for more than 500 µs.

The PWRGD pin will go low if the output is outside the regula-

tion band for more than 500

µs.

Output Crowbar

An added feature of using an N-channel MOSFET as the syn-

chronous switch is the ability to crowbar the output with the

same MOSFET. If the output voltage is 15% greater than the

targeted value, the ADP3155 will turn on the lower MOSFET,

which will current-limit the source power supply or blow its

fuse, pull down the output voltage, and thus save the micropro-

cessor from destruction. The crowbar function releases at ap-

proximately 50% of the nominal output voltage. For example, if

the output is programmed to 2.0 V, but is pulled up to 2.3 V or

above, the crowbar will turn on the lower MOSFET. If in this

case the output is pulled down to less than 1.0 V, the crowbar

will release, allowing the output voltage to recover to 2.0 V if

the fault condition has been removed.

Shutdown

The ADP3155 has a shutdown (SD) pin that is pulled down by

an internal resistor. In this condition the device functions nor-

mally. This pin should be pulled high to disable the output drives.

APPLICATION INFORMATION

A number of power conversion requirements must be consid-

ered when designing an ACPI compliant system. In normal

operating mode, 12 V, 5 V and 3.3 V are available from the

main supply. These voltages need to be converted into the

appropriate supply voltages for the Northbridge core, the

Southbridge core and RAMBUS memory, as well as supplies for

GTL and I/O drivers, CMOS memory and clock and graphics

(AGP) circuits.

During the standby operating state, the 12 V, 5 V and 3.3 V

power supply outputs are disabled, and only a low power 5 V

rail (5VSB) is available. The circuits that must remain active in

standby must be able to run from 5VSB. To accomplish this,

power routing is required to allow switching between normal

and standby supplies. Lack of a 12 V rail in standby makes control

of linear outputs difficult, and with up to 8 A demand from the

1.5 V and 1.8 V rails, an all-linear solution is inefficient.

Figure 14 shows a typical ACPI-compliant Pentium III/chipset

power management system using the ADP3155 and ADP3156.

The ADP3155 provides VID switched output and two linear

regulators for standby operation. A charge-pump-doubled 5VSB is

ORed into the supply rail to supply the linear regulators during

standby operation. The VID output collapses when the main

5 V rail collapses, but the N-channel MOSFET linear regu-

lators can continue to supply current from the ~9 V supply.

The ADP3156 provides 1.8 V via its main switching regulator,

and allows efficient linear regulation of 1.5 V rail by using the

1.8 V output as its source.

Specifications for a Design Example

The design parameters for a typical 300 MHz Pentium II appli-

cation (Figure 2) are as follows:

Maximum Output Current:

Minimum Output Current:

Static tolerance of the supply voltage for the processor core:

∆V

∆V

5V_PM

POWER

MANAGEMENT

FUNCTIONS

12V

POWER MANAGEMENT

STATE COMMAND

5V_PM

ATX_POWER GOOD

PMSC

5V_PM

ATXPG

ADP3155

VID_4:0

LIN#2_

CTRLS

LIN#1_

CTRLS

MAIN_

CTRLS

SWITCHER

IN

CTRLS

OUT

LINEAR#1

IN

CTRLS

OUT

LINEAR#2

IN

CTRLS

OUT

5V

5V_PM

CPU

3.3V_PM

FOR POWER

MANAGEMENT

2.5V_PM

FOR CMOS,

CLOCK, MEMORY

TRIPLE

OUTPUT

SUPPLY

VID

ADP3156

LIN_

CTRLS

MAIN_

CTRLS

12V

DUAL

OUTPUT

SUPPLY

IN

CTRLS

OUT

SWITCHER

5V

IN

CTRLS

OUT

LINEAR

3.3V_IN

1.5V_IN

VDDQ

POWER ROUTING

SELECT

3.3V

1.8V FOR

SB CORE,

MEM, ETC

1.5V VTT

FOR GTL

1.5V OR 3.3V

VDDQ FOR AGP

TYPEDET# FOR

AGP SELECT

ATX

(OR NLX)

POWER

SUPPLY

12V

5V

3.3V

5V_ALWAYS

ATX_PGOOD

ATX_SHUTDOWN

GND

12V

5V

3.3V

5V_PM

ATX_POWERGOOD

ATX_SHUTDOWN

Figure 14. ACPI-Compliant Pentium III System Block Diagram