REV. A

ADP3155

–11–

amplifier output, with the lower resistor tied to ground and the

upper resistor to the 12 V supply of the IC. The values of these

resistors can be calculated using:

RR

V

V

UPPER

C

DIV

OS

=×

and:

RR

V

VV

LOWER

C

OS

DIV

OS

=×

–

the nominal VID-programmed value to the center of the speci-

fied regulation window for the output voltage. (Note this may be

either positive or negative.) For clarification, that offset is given

by:

VV

V

VID

OUT OS

HI

LO

()

()–

=+

1

2

allowed for regulation.

Finally, the compensating capacitance is determined from the

equality of the pole frequency of the error amplifier gain and the

zero frequency of the impedance of the output capacitor:

C

C

ESR

Rt

COMP

O

TOTAL

=

×

Trade-Offs Between DC Load Regulation and AC Load

Regulation

Casual observation of the circuit operation—e.g., with a voltmeter

—would make it appear that the dc load regulation appears

to be rather poor compared to a conventional regulator. This

would be especially noticeable under very light or very heavy

loads where the voltage is “positioned” near one of the extremes

of the regulation window rather than near the nominal center

value. It must be noted and understood that this low gain char-

acteristic (i.e., loose dc load regulation) is inherently required to

allow improved transient containment (i.e., to achieve tighter ac

load regulation). That is, the dc load regulation is intentionally

sacrificed (but kept within specification) in order to minimize

the number of capacitors required to contain the load transients

produced by the CPU.

Linear Regulators

The two ADP3155 linear regulators provide a low cost, conve-

nient and versatile solution for generating additional lower sup-

ply rails that can be programmed in the range 1.2 V–5 V. The

maximum output load current is determined by the size and

thermal impedance of the external N-channel power MOSFET

that is placed in series with the supply and controlled by the

at the FB pin of the ADP3155 and compared to an internal

1.2 V reference in a negative feedback loop which keeps the

output voltage in regulation. If the load is being reduced or

increased, the FET drive will also be reduced or increased by the

ADP3155 to provide a well regulated

±1% accurate output

voltage. The output voltage is programmed by adjusting the

Efficiency of the Linear Regulators

The efficiency and corresponding power dissipation of each of

the linear regulators are not determined by the ADP3155.

Rather, these are a function of input and output voltage and

load current. Efficiency is approximated by the formula:

η = 100% × (V

OUT

The corresponding power dissipation in the MOSFET, together

with any resistance added in series from input to output is given

by:

Minimum power dissipation and maximum efficiency are ac-

complished by choosing the lowest available input voltage that

exceeds the desired output voltage. However, if the chosen

input source is itself generated by a linear regulator, its power

dissipation will be increased in proportion to the additional

current it must now provide. For most PC systems, the lowest

available input source for the linear regulators, which is not

itself generated by a linear regulator, is 3.3 V from the main

power supply.

Assuming that the 3.3 V supply is used to provide input power

for a 1.5 V linear regulator output, the efficiency will inherently

be 1.5 V

3.3 V, which is less than 50%. The total current

demand in all of the low voltage power rails (e.g., 1.5 V, 1.8 V

and 2.5 V) can produce unacceptable dissipation and junction

temperatures in the linear regulators. For such systems, Analog

Devices recommends the ADP3156—a switching regulator that

generates one of the lower voltage outputs (e.g., 1.8 V), which can

also be used as a power source to the lower voltage outputs

(e.g., 1.5 V). This results is a highly efficient and reliable power

conversion system that can readily handle the combined loading

specifications for the lower system voltages, with room to spare

for the higher current demands and lower voltages of next gen-

eration PC systems.

Features

• Tight DC Regulation Due to 1% Reference and High Gain

• Output Voltage Stays Within Specified Limits at Load

Current Step with 30 A/

µs Slope

• Fast Response to Input Voltage or Load Current Transients

Overcurrent protection may be provided by the addition of an

specification and procedure is given below.

V

R

Rt

VV

Rt

k

V

Rt

k

RI

OS

C

TOTAL

OUT OS

TOTAL

TOTAL

CS OMAX

=×

+

















+

















08

136

17

275

6

.

.

–.

()

ΩΩ

(2)