REV. A

ADP3155

–13–

8.

The output capacitors should also be connected as closely

as possible to the load (or connector) that receives the

power (e.g., a microprocessor core). If the load is distrib-

uted, the capacitors also should be distributed, and gen-

erally in proportion to where the load tends to be more

dynamic.

9.

Absolutely avoid crossing any signal lines over the switching

power path loop, described below.

Power Circuitry

10. The switching power path should be routed on the PCB to

encompass the smallest possible area in order to minimize

radiated switching noise energy (i.e., EMI). Failure to take

proper precaution often results in EMI problems for the

entire PC system as well as noise-related operational prob-

lems in the power converter control circuitry. The switching

power path is the loop formed by the current path through

the input capacitors, the two FETs and the power Schottky

diode, if used, including all interconnecting PCB traces and

planes. The use of short and wide interconnection traces is

especially critical in this path for two reasons: it minimizes

the inductance in the switching loop, which can cause high-

energy ringing, and it accommodates the high current de-

mand with minimal voltage loss.

11. A power Schottky diode (1 ~ 2 A dc rating) placed from the

lower FET’s source (anode) to drain (cathode) will help to

minimize switching power dissipation in the upper FET. In

the absence of an effective Schottky diode, this dissipation

occurs through the following sequence of switching events.

The lower FET turns off in advance of the upper FET

turning on (necessary to prevent cross-conduction). The

circulating current in the power converter, no longer find-

ing a path for current through the channel of the lower

FET, draws current through the inherent body-drain diode

of the FET. The upper FET turns on, and the reverse

recovery characteristic of the lower FET’s body-drain diode

prevents the drain voltage from being pulled high quickly.

The upper FET then conducts very large current while it

momentarily has a high voltage forced across it, which

translates into added power dissipation in the upper FET.

The Schottky diode minimizes this problem by carrying a

majority of the circulating current when the lower FET is

turned off, and by virtue of its essentially nonexistent re-

verse recovery time.

12. A small ferrite bead inductor placed in series with the drain

of the lower FET can also help to reduce this previously

described source of switching power loss.

13. Whenever a power dissipating component (e.g., a power

MOSFET) is soldered to a PCB, the liberal use of vias,

both directly on the mounting pad and immediately sur-

rounding it, is recommended. Two important reasons for

this are: improved current rating through the vias (if it is a

current path), and improved thermal performance—espe-

cially if the vias extended to the opposite side of the PCB

where a plane can more readily transfer the heat to the air.

14. The output power path, though not as critical as the switch-

ing power path, should also be routed to encompass a small

area. The output power path is formed by the current path

through the inductor, the current sensing resistor, the out-

put capacitors, and back to the input capacitors.

15. For best EMI containment, the power ground plane should

extend fully under all the power components except the

output capacitors. These are: the input capacitors, the

power MOSFETs and Schottky diode, the inductor, the

current sense resistor and any snubbing elements that

might be added to dampen ringing. Avoid extending the

power ground under any other circuitry or signal lines,

including the voltage and current sense lines.

Signal Circuitry

16. The output voltage is sensed and regulated between the

AGND pin (which connects to the signal ground plane)

and the SENSE– pin. The output current is sensed (as a

voltage) and regulated between the SENSE– pin and the

SENSE+ pin. In order to avoid differential mode noise

pickup in those sensed signals, their loop areas should be

small. Thus the SENSE– trace should be routed atop the

signal ground plane, and the SENSE+ and SENSE– traces

should be routed as a closely coupled pair (SENSE+ should

be over the signal ground plane as well).

17. The SENSE+ and SENSE– traces should be Kelvin con-

nected to the current sense resistor so that the additional

voltage drop due to current flow on the PCB at the current

sense resistor connections does not affect the sensed volt-

age. It is desirable to have the ADP3155 close to the output

capacitor bank and not in the output power path, so that

any voltage drop between the output capacitors and the

AGND pin is minimized, and voltage regulation is not

compromised.