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ADP3408 Datasheet(PDF) 15 Page - Analog Devices |
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ADP3408 Datasheet(HTML) 15 Page - Analog Devices |
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15 / 16 page ![]() REV. 0 ADP3408 –15– Appropriate sense resistors are available from the following vendors: Vishay Dale IRC Panasonic Charger FET Selection The type and size of the pass transistor is determined by the threshold voltage, input-output voltage differential, and the charge current. The selected PMOS must satisfy the physical, electrical and thermal design requirements. To ensure proper operation, the minimum VGS the ADP3408 can provide must be enough to turn on the FET. The available gate drive voltage can be estimated using the following: VV V V GS ADAPTER MIN GATEDR SENSE =− − () (8) where: VADAPTER(MIN) is the minimum adapter voltage, VGATEDR is the gate drive “low” voltage, 0.5 V, and VSENSE is the maximum high current limit threshold voltage. The difference between the adapter voltage (VADPTER) and the final battery voltage (VBAT) must exceed the voltage drop due to the blocking diode, the sense resistor, and the ON resistance of the FET at maximum charge current, where: VV V V V DS ADAPTER MIN DIODE SENSE BAT =− − − () (9) The RDS(ON) of the FET can then be calculated. R V I DS ON DS CHR MAX () () = (10) The thermal characteristics of the FET must be considered next. The worst-case dissipation can be determined using: P V V V UVLO I DISS ADAPTER MAX DIODE SENSE CHR =− − − ()× () (11) It should be noted that the adapter voltage can be either preregulated or nonregulated. In the preregulated case the difference between the maximum and minimum adapter voltage is probably not significant. In the unregulated case, the adapter voltage can have a wide range specified. However, the maximum voltage specified is usually with no load applied. So, the worst-case power dissipation calculation will often lead to an over-specified pass device. In either case, it is best to determine the load characteristics of the adapter to optimize the charger design. For example: VADAPTER(MIN) = 5.0 V VADAPTER(MAX) = 6.5 V VDIODE = 0.5 V at 800 mA VSENSE = 160 mV VGATEDR = 0.5 V VGS = 5 V – 0.5 V – 160 V = 4.34 V Therefore, choose a low threshold voltage FET. VV V V V VV V V mV R V I mV mA m P V V V UVLO I PV V V A DS ADAPT MIN DIODE SENSE BAT DS ON DS CHR MAX DISS ADAPT MAX DIODE SENSE CHR DISS == = == = = ()× = ()×= () () () () –– – – . – . – . –– – . – . – . – .. . 5 0 5 0 160 4 2 140 140 800 175 65 05 0160 32 08 211 Ω W W Appropriate PMOS FETs are available from the following vendors: Siliconix IR Fairchild Charger Diode Selection The diode, D1, shown in Figure 2, is used to prevent the battery from discharging through the PMOS’ body diode into the charger’s internal bias circuits. Choose a diode with a current rating high enough to handle the battery charging current and a voltage rating greater than VBAT. The blocking diode is required for both lithium and nickel battery types. Printed Circuit Board Layout Considerations Use the following general guidelines when designing printed circuit boards: 1. Connect the battery to the VBAT, VBAT2, and VRTCIN pins of the ADP3408. Locate the input capacitor as close to the pins as possible. 2. VAN and VTCXO capacitors should be returned to AGND. 3. VCORE, VMEM and VSIM capacitors should be returned to DGND. 4. Split the ground connections. Use separate traces or planes for the analog, digital, and power grounds and tie them together at a single point, preferably close to the battery return. 5. Run a separate trace from the BATSNS pin to the battery to prevent voltage drop error in the MVBAT measurement. 6. Kelvin-connect the charger’s sense resistor by running sepa- rate traces to the CHRIN and ISENSE pins. Make sure that the traces are terminated as close to the resistor’s body as possible. 7. Use the best industry practice for thermal considerations during the layout of the ADP3408 and charger components. Careful use of copper area, weight, and multilayer construc- tion all contribute to improved thermal performance. |
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