ADSP-2191 datasheet(28/52 Pages) AD

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ADSP-2191M

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REV. 0

Host Port ACC Mode Write Cycle Timing

Table 16 and Figure 15 describe Host port write operations in Address Cycle Control (ACC) mode. For more information on ACK,

Ready, ALE, and ACC mode selection, see the Host port modes description on page 8.

Table 16. Host Port ACC Mode Write Cycle Timing

Parameter

Min

Max

Unit

Switching Characteristics

tWHKS1

HWR Asserted to HACK Asserted (ACK Mode) First Byte

5tHCLK+tNH

NH are peripheral bus latencies (n

tHCLK); these are internal DSP latencies related to the number of peripheral DMAs attempting to access DSP memory

at the same time.

tWHKS2

HWR Asserted to HACK Asserted (Setup, ACK Mode)2

2 Measurement is for the second, third, or fourth byte of a host write transaction. The quantity of bytes to complete a host write transaction is dependent

on the data bus size (8 or 16 bits) and the data type (16 or 24 bits).

tWHKH

HWR Deasserted to HACK Deasserted (Hold, ACK Mode)

tWHS

HWR Asserted to HACK Asserted (Setup, Ready Mode)

tWHH

HWR Asserted to HACK Deasserted (Hold, Ready Mode)

First Byte

05tHCLK+tNH

tWSHKS

HWR Asserted to HACK Asserted (Setup) During Address

Latch

tWHHKH

HWR Deasserted to HACK Deasserted (Hold) During

Address Latch

Timing Requirements

tWAL

HWR Asserted to HALE Deasserted (Delay)

1.5

tCSAL

HCMS or HCIOMS Asserted to HALE Asserted (Delay)

0ns

tALCS

HALE Deasserted to Optional

HCMS or HCIOMS

Deasserted

1ns

tWCSW

HWR Deasserted to HCMS or HCIOMS Deasserted

tALW

HALE Asserted to HWR Asserted

0.5

tCSW

HCMS or HCIOMS Asserted to HWR Asserted

0ns

tWCS

HWR Deasserted (After Last Byte) to HCMS or

HCIOMS Deasserted (Ready for Next Write)

0ns

tALEW

HALE Deasserted to HWR Asserted

tHKWD

HACK Asserted to

HWR Deasserted (Hold, ACK Mode)

1.5

tADW

Address Valid to

HWR Asserted (Setup)

tWAD

HWR Deasserted to Address Invalid (Hold)

tDWS

Data Valid to

HWR Deasserted (Setup)

tWDH

HWR Deasserted to Data Invalid (Hold)

tHKWAL

HACK Asserted to

HWR Deasserted (Hold) During Address

Latch

2ns

ADSP-2191 Datasheet(PDF) 28 Page - Analog Devices

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