RT8015 datasheet(12/15 Pages) RICHTEK

12 / 15 page

RT8015

DS8015-03

March 2011

www.richtek.com

Efficiency Considerations

The efficiency of a switching regulator is equal to the output

power divided by the input power times 100%. It is often

useful to analyze individual losses to determine what is

limiting the efficiency and which change would produce

the most improvement. Efficiency can be expressed as :

Efficiency = 100%

− (L1+ L2+ L3+ ...) where L1, L2, etc.

are the individual losses as a percentage of input power.

Although all dissipative elements in the circuit produce

losses, two main sources usually account for most of the

losses: VDD quiescent current and I

2R losses.

The VDD quiescent current loss dominates the efficiency

loss at very low load currents whereas the I

2R loss

dominates the efficiency loss at medium to high load

currents. In a typical efficiency plot, the efficiency curve

at very low load currents can be misleading since the

actual power lost is of no consequence.

1. The VDD quiescent current is due to two components :

the DC bias current as given in the electrical characteristics

and the internal main switch and synchronous switch gate

charge currents. The gate charge current results from

switching the gate capacitance of the internal power

MOSFET switches. Each time the gate is switched from

high to low to high again, a packet of charge

∆Q moves

from VDD to ground. The resulting

∆Q/∆t is the current out

of VDD that is typically larger than the DC bias current. In

continuous mode, IGATECHG= f(QT+QB) where QT and QB

are the gate charges of the internal top and bottom

switches.

Both the DC bias and gate charge losses are proportional

to VDD and thus their effects will be more pronounced at

higher supply voltages.

2. I

2R losses are calculated from the resistances of the

internal switches, RSW and external inductor RL. In

continuous mode the average output current flowing

through inductor L is

“chopped” between the main switch

and the synchronous switch. Thus, the series resistance

looking into the LX pin is a function of both top and bottom

MOSFET RDS(ON) and the duty cycle (D) as follows :

RSW = RDS(ON)TOP x D + RDS(ON)BOT x (1"D) The RDS(ON)

for both the top and bottom MOSFETs can be obtained

from the Typical Performance Characteristics curves. Thus,

to obtain I

2R losses, simply add RSW to RL and multiply

the result by the square of the average output current.

Other losses including CIN and COUT ESR dissipative

losses and inductor core losses generally account for less

than 2% of the total loss.

Checking Transient Response

The regulator loop response can be checked by looking

at the load transient response. Switching regulators take

several cycles to respond to a step in load current. When

a load step occurs, VOUT immediately shifts by an amount

equal to

∆ILOAD(ESR), where ESR is the effective series

resistance of COUT.

∆ILOAD also begins to charge or

discharge COUT generating a feedback error signal used

by the regulator to return VOUT to its steady-state value.

During this recovery time, VOUT can be monitored for

overshoot or ringing that would indicate a stability problem.

The COMP pin external components and output capacitor

shown in Typical Application Circuit will provide adequate

compensation for most applications.

Thermal Considerations

For continuous operation, do not exceed absolute

maximum operation junction temperature 125

°C.

The maximum power dissipation depends on the thermal

resistance of IC package, PCB layout, the rate of

surroundings airflow and temperature difference between

junctions to ambient. The maximum power dissipation can

be calculated by following formula:

PD(MAX) = ( TJ(MAX)

− TA ) / θJA

Where TJ(MAX) is the maximum operation junction

temperature 125

°C, TAis the ambient temperature and the

θJA is the junction to ambient thermal resistance.

For recommended operating conditions specification of

RT8015, where TJ(MAX) is the maximum junction

temperature of the die (125

°C) and TA is the maximum

ambient temperature. The junction to ambient thermal

resistance for SOP-8 (Exposed Pad) package is 75

°C/W

on the standard JEDEC 51-7 (4 layers, 2S2P) thermal

test board. The copper thickness is 2oz. The maximum

power dissipation at TA = 25

°C can be calculated by

following formula:

PD (MAX) = (125

°C − 25°C) / (75°C/W) = 1.33W (SOP-8

Exposed Pad on the minimum layout)

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