LTC3375 datasheet(29/36 Pages) LINER

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LTC3375

3375fa

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applicaTions inForMaTion

In general the circuit in 6a is recommended if the appli-

cation needs to drive any external circuitry with VCC or if

the larger compensation capacitor is tolerable. If VCC is

only needed to drive the LTC3375 and smaller component

sizes are critical, then the circuit in Figure 6b may be used.

Input and Output Decoupling Capacitor Selection

TheLTC3375hasindividualinputsupplypinsforeachbuck

switching regulator. Each of these pins must be decoupled

withlowESRcapacitorstoGND.Thesecapacitorsmustbe

placed as close to the pins as possible. Ceramic dielectric

capacitorsareagoodcompromisebetweenhighdielectric

constant and stability versus temperature and DC bias.

Note that the capacitance of a capacitor deteriorates at

higher DC bias. It is important to consult manufacturer

data sheets and obtain the true capacitance of a capacitor

at the DC bias voltage it will be operated at. For this rea-

son, avoid the use of Y5V dielectric capacitors. The X5R/

X7R dielectric capacitors offer good overall performance.

The input supply voltage Pins 2, 5, 8, 11, 26, 29, 32 and

35 all need to be decoupled with at least 10µF capacitors.

Choosing the CT Capacitor

The CT capacitor may be used to program the timing

parameters associated with the pushbutton. For a given

CT capacitor the timing parameters may be calculated as

below. CT is in units of µF.

tPB_LO = 5000 • CT ms

tPB_ON = 20000 • CT ms

tPB_OFF = 1000 • CT seconds

tHR = 100 • CT seconds

tIRQ_PW = 5000 • CT ms

tKILLH = 1000 • CT seconds

tKILLL = 5000 • CT ms

tRST = 23000 • CT ms

Programming the Global Register

The Global Register contains functions that either act on

the LTC3375 top level or act on all buck switching regula-

tors at once. These functions are described in Table 8. The

default structure is ‘0000 0000b’.

Programming the RST and IRQ Mask Registers

The RST mask register can be programmed by the user

at sub-address 09h and its format is shown in Table 9.

If a bit is set to ‘1’, then the corresponding regulator’s

PGOOD will pull RST low if a PGOOD fault were to occur.

The default for this register is FFh.

The IRQ mask registers have the same bit format as the

RST mask register. The IRQ mask registers are located at

sub-addresses 0Ah and 0Bh and their default contents

are 00h.

Status Byte Read Back

When either the RST or IRQ pin is pulled low, it indicates

to the user that a fault condition has occurred. To find out

the exact nature of the fault, the user can read the status

registers. There are three registers that contain status

information. The register at sub-address 0Ch provides

PGOOD fault condition reporting, while the register at

sub-address0DhprovidesUVLOfaultconditionreporting.

These bits are all latched at interrupt. If any of the bits

are disabled via masking, then their real time, unlatched

status information is still available. Bit7 of the register

at sub-address 0Eh provides latched information on the

status of the DT Warning. Figure 4 shows the operation

of the status registers. The contents of the IRQ status

PGOOD bit is a ‘0’ if the regulator’s output voltage is more

than 7.5% below its programmed value. A UVLO bit is a

‘0’ if the associated VIN is above its input UVLO threshold.

The format for the status registers is shown in Table 10.

A write operation cannot be performed to any of these

status registers.

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