LTC3375

30

3375fa

For more information www.linear.com/3375

Table 8. Global Control Program Register Bit Format

Bit7

RESET_ALL

Default is ‘0’. When asserted all buck converters will power down for 1 second after which the bit will clear itself.

Bit6(DT1)

Bit5(DT0)

DT WARNING

CONTROL

Default is ‘00’ which deactivates the DT warning. ‘01’ programs –140°, ‘10’ programs –125°,

and ‘11’ programs –110°.

Bit4

IGNORE_EN

Default is ‘0’ which allows the EN pins to power on the buck converters. When written to ‘1’ the enable pins will be

Bit3

1KPD

Default is ‘0’ in which the SW node remains in a high impedance state when the regulator is in shutdown. A ‘0’ pulls

the SW node to GND through a 10k resistor. This bit acts on all buck converters at once.

Bit2

SLOW EDGE

This bit controls the slew rate of the switch node. Default is ‘0’ which enables the switch node to slew at a faster

rate, than if the bit were programmed a ‘1’. This bit acts on all buck converters at once.

Bit1

RD_TEMP

Default is ‘0’. This bit commands the temperature A/D to sample the voltage present at the TEMP pin. After a read is

complete this bit will clear itself.

Bit0

Unused

This bit is unused and must be written to “0”

applicaTions inForMaTion

Table 9

BIT7

BIT6

BIT5

BIT4

BIT3

BIT2

BIT1

BIT0

PGOOD[8]

PGOOD[7]

PGOOD[6]

PGOOD[5]

PGOOD[4]

PGOOD[3]

PGOOD[2]

PGOOD[1]

Table 10

Sub-

Address

BIT7

BIT6

BIT5

BIT4

BIT3

BIT2

BIT1

BIT0

0Ch

PGOOD[8] PGOOD[7] PGOOD[6] PGOOD[5] PGOOD[4] PGOOD[3] PGOOD[2]

PGOOD[1]

0Dh

UVLO[8]

UVLO[7]

UVLO[6]

UVLO[5]

UVLO[4]

UVLO[3]

UVLO[2]

UVLO[1]

0Eh

DT_WARN TEMP[6]

TEMP[5]

TEMP[4]

TEMP[3]

TEMP[2]

TEMP[1]

TEMP[0]

PCB Considerations

When laying out the printed circuit board, the following

list should be followed to ensure proper operation of the

LTC3375:

1. Theexposedpadofthepackage(Pin49)shouldconnect

directly to a large ground plane to minimize thermal and

electrical impedance.

2. All the input supply pins should each have a decoupling

capacitor.

3. Theconnectionstotheswitchingregulatorinputsupply

pins and their respective decoupling capacitors should

be kept as short as possible. The GND side of these

capacitors should connect directly to the ground plane

of the part. These capacitors provide the AC current

to the internal power MOSFETs and their drivers. It is

importanttominimizeinductancefromthesecapacitors

4. The switching power traces connecting SW1, SW2,

SW3, SW4, SW5, SW6, SW7 and SW8 to their respec-

tive inductors should be minimized to reduce radiated

EMI and parasitic coupling. Due to the large voltage

swing of the switching nodes, high input impedance

sensitive nodes, such as the feedback nodes, should

be kept far away or shielded from the switching nodes

or poor performance could result.

5. The GND side of the switching regulator output capaci-

torsshouldconnectdirectlytothethermalgroundplane

of the part. Minimize the trace length from the output

capacitor to the inductor(s)/pin(s).

6. Inacombinedbuckregulatorapplicationthetracelength

of switch nodes to the inductor must be kept equal to

ensure proper operation.