LT3757 datasheet(7/24 Pages) LINER

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LT3959

3959f

PIN FUNCTIONS

DRIVE (Pin 28): DRIVE LDO Supply Pin. This pin can be

connected to either VIN or a quasi-regulated voltage supply

such as a DC converter output. This pin must be bypassed

to GND with a minimum of 1μF capacitor placed close to

the pin. Tie this pin to VIN if not used.

EN/UVLO (Pin 25): Shutdown and Undervoltage Detect

Pin. An accurate 1.22V (nominal) falling threshold with

externally programmable hysteresis detects when power

is okay to enable switching. Rising hysteresis is generated

by the external resistor divider and an accurate internal

2.2μA pull-down current. An undervoltage condition resets

soft-start. Tie to 0.4V, or less, to disable the device and

reduce VIN quiescent current below 1μA.

FBX (Pin 31): Voltage Regulation Feedback Pin for Positive

or Negative Outputs. Connect this pin to a resistor divider

between the output and SGND. FBX is the input of two error

amplifiers—one configured to regulate a positive output;

the other, a negative output. Depending upon topology

selected, switching causes the output to ramp positive or

negative. The appropriate amplifier takes control while the

other becomes inactive. Additionally FBX is input for two

window comparators that indicate through the PGOOD

pin when the output is within 5% of the regulation volt-

ages. FBX also modulates the switching frequency during

start-up and fault conditions when FBX is close to SGND.

GND (Pins 13-17): Source Terminal of Switch and the GND

Input to the Switch Current Comparator.

GNDK (Pin 12): Kelvin Connection Pin between GND and

SGND. Kelvin connect this pin to the SGND plane close

to the IC. See the Board Layout section.

INTVCC (Pin 36): Regulated Supply for Internal Loads and

Gate Driver. Regulated to 4.75V if powered from DRIVE

or regulated to 3.75V if powered from VIN. The INTVCC

pin must be bypassed to SGND with a minimum of 4.7μF

capacitor placed close to the pin.

NC (Pins 1-3, 6, 10, 23): No Internal Connection. Leave

these pins open or connect them to the adjacent pins.

PGOOD (Pin 35): Output Ready Status Pin. An open-

collector pull down on PGOOD asserts when INTVCC is

greater than 2.7V and the FBX voltage is within 5% (80mV

if VFBX = 1.6V or 40mV if VFBX = –0.8V) of the regulation

voltage.

RT (Pin 33): Switching Frequency Adjustment Pin. Set

the frequency using a resistor to SGND. Do not leave the

RT pin open.

SGND (Exposed Pad Pin 37, Pins 4, 24): Signal Ground.

Must be soldered directly to the signal ground plane.

Connect to ground terminal of: external resistor dividers

for FBX and EN/UVLO; capacitors for INTVCC, SS, and VC;

and resistor RT.

SS (Pin 32): Soft-Start Pin. This pin modulates compensa-

tion pin voltage (VC) clamp. The soft-start interval is set

with an external capacitor. The pin has a 10μA (typical)

pull-up current source to an internal 2.5V rail. The soft-

start pin is reset to SGND by an EN/UVLO undervoltage

condition, an INTVCC undervoltage condition or an internal

thermal lockout.

SW (Exposed Pad Pin 38, Pins 8, 9, 20, 21): Drain of

Internal Power N-Channel MOSFET.

SYNC (Pin 34): Frequency Synchronization Pin. Used to

synchronize the internal oscillator to an outside clock. If

this feature is used, an RT resistor should be chosen to

program a switching frequency 20% slower than SYNC

pulse frequency. Tie the SYNC pin to SGND if this feature

is not used. This signal is ignored during FB frequency

foldback or when INTVCC is less than 2.7V.

VIN (Pin 27): Supply Pin for Internal Leads and the VIN

LDO Regulator of INTVCC. Must be locally bypassed to GND

with a minimum of 1μF capacitor placed close to this pin.

VC (Pin 30): Error Amplifier Compensation Pin. Used to

stabilize the voltage loop with an external RC network. Place

compensation components between the VC pin and SGND.

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