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LT3959

3959f

APPLICATIONS INFORMATION

Main Control Loop

The LT3959 uses a fixed frequency, current mode control

scheme to provide excellent line and load regulation.

Operation can be best understood by referring to the Block

Diagram in Figure 1.

The start of each oscillator cycle sets the SR latch (SR1)

and turns on the internal power MOSFET switch M1 through

driver G2. The switch current flows through the internal

current sensing resistor RSENSE and generates a voltage

proportional to the switch current. This current sense

voltage VISENSE (amplified by A5) is added to a stabilizing

slope compensation ramp and the resulting sum (SLOPE)

is fed into the positive terminal of the PWM comparator A7.

When SLOPE exceeds the level at the negative input of A7

(VC pin), SR1 is reset, turning off the power switch. The

level at the negative input of A7 is set by the error amplifier

A1 (or A2) and is an amplified version of the difference

between the feedback voltage (FBX pin) and the reference

voltage (1.6V or –0.8V, depending on the configuration).

In this manner, the error amplifier sets the correct peak

switch current level to keep the output in regulation.

The LT3959 has a switch current limit function. The cur-

rent sense voltage is input to the current limit comparator

A6. If the SENSE voltage is higher than the sense current

limit threshold VSENSE(MAX) (45mV, typical), A6 will reset

SR1 and turn off M1 immediately.

The LT3959 is capable of generating either positive or

negative output voltage with a single FBX pin. It can be

configured as a boost or SEPIC converter to generate

positive output voltage, or as an inverting converter to

generate negative output voltage. When configured as a

SEPIC converter, as shown in Figure 1, the FBX pin is pulled

up to the internal bias voltage of 1.6V by a voltage divider

(R1 and R2) connected from VOUT to SGND. Comparator

A2 becomes inactive and comparator A1 performs the

inverting amplification from FBX to VC. When the LT3959 is

in an inverting configuration, the FBX pin is pulled down to

–0.8V by a voltage divider connected from VOUT to SGND.

Comparator A1 becomes inactive and comparator A2

performs the noninverting amplification from FBX to VC.

The LT3959 has overvoltage protection functions to protect

the converter from excessive output voltage overshoot

during start-up or recovery from a short-circuit condition.

An overvoltage comparator A11 (with 40mV hysteresis)

senses when the FBX pin voltage exceeds the positive

regulated voltage (1.6V) by 7.5% and turns off M1.

Similarly, an overvoltage comparator A12 (with 20mV

hysteresis) senses when the FBX pin voltage exceeds the

negative regulated voltage (–0.8V) by 7.5% and turns

off M1. Both reset pulses are sent to the main RS latch

(SR1) through G6 and G5. The internal power MOSFET

switch M1 is actively held off for the duration of an output

overvoltage condition.

Programming Turn-On and Turn-Off Thresholds with

EN/UVLO Pin

The EN/UVLO pin controls whether the LT3959 is enabled

or is in shutdown state. A micropower 1.22V reference, a

comparator A10 and controllable current source IS1 allow

the user to accurately program the supply voltage at which

the IC turns on and off. The falling value can be accurately

set by the resistor dividers R3 and R4. When EN/UVLO

is above 0.7V, and below the 1.22V threshold, the small

pull-down current source IS1 (typical 2.2μA) is active.

The purpose of this current is to allow the user to program

the rising hysteresis. The Block Diagram of the comparator

and the external resistors is shown in Figure 1. The typical

falling threshold voltage and rising threshold voltage can

be calculated by the following equations:

VVIN(FALLING) = 1.22 •

(R3

+R4)

VVIN(RISING) =2.2μA • R3+ VIN(FALLING)

For applications where the EN/UVLO pin is only used as

a logic input, the EN/UVLO pin can be connected directly

to the input voltage VIN for always-on operation.

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