Aeroflex Circuit Technology

32

SCDCT2553 REV B 8/6/99 Plainview NY (516) 694-6700

45

D09

(5)

-0.4

-400

3.6

I/O Data Bus Bit 9.

46

D11

(5)

-0.4

-400

3.6

I/O Data Bus Bit 11.

47

D13

(5)

-0.4

-400

3.6

I/O Data Bus Bit 13.

48

D15

(5)

-0.4

-400

3.6

I/O Data Bus Bit 15 (MSB).

49

RTAD3

(5)

-0.4

-

-

Remote Terminal Address Bit 3.

50

RTAD2

(5)

-0.4

-

-

Remote Terminal Address Bit 2.

51

RTADP

(5)

-0.4

-

-

Remote Terminal Address Parity input.

52

SA/MC-2

-

-

-400

2.0

Subaddress/Mode Command Bit 2. B8 (MSB) counter.

53

SA/MC-4

-

-

-400

2.0

Subaddress/Mode Command Bit 4.

54

SA/MC-3

-

-

-400

2.0

Subaddress/Mode Command Bit 3.

55

THIS-RT

-

-

-400

2.0

Logic 0 pulse indicates receipt of a valid command word which contains

the Remote Terminal address equivalent to the RTADO-RTAD4 inputs.

56

RTPARERR

-

-

-400

2.0

RTU (address) Parity Error. Logic 0 indicates RTU address parity (odd

parity: RTADO-RTAD4, RTADP) has been violated.

57

T/R

-

-

-400

2.0

Transmit/Receive 1553 data. Latched T/R bit from current command

word.

58

+5VB

-

-

-

-

+5V power supply connection for the B channel transceiver.

59

TX/RX-B

-

-

-

-

Transmit/Receive transceiver-B. Inverted I/O to coupling transformer

that connects to channel B of the 1553 Bus.

60

A00

(5)

-0.4

-400

3.6

Address Bit 0 (LSB).

61

A02

(5)

-0.4

-400

3.6

Address Bit 2.

62

A04

(5)

-0.4

-400

3.6

Address Bit 4.

63

A06

(5)

-0.4

-400

3.6

Address Bit 6.

64

A08

(5)

-0.4

-400

3.6

Address Bit 8.

65

A10

(5)

-0.4

-400

3.6

Address Bit 10.

66

A12

(5)

-0.4

-400

3.6

Address Bit 12.

67

A14

(5)

-0.4

-400

3.6

Address Bit 14.

68

MEMWR

-

-

-400

4.0

Memory Write. Output pulse to write data into memory.

69

MEMENA-IN

±20

±0.02

-

-

Memory Enable In. Enables internal RAM only; connect directly to

MEMENA-OUT.

70

INCMD

-

-

-400

2.0

In Command. Indicates BC or RTU currently in message transfer

sequence.

71

MSTRCLR

(6)

-0.7

-

-

Master Clear. Power-on reset from CPU.

72

INT

-

-

-400

4.0

Interrupt. Interrupt pulse line to CPU.

73

IOEN

-

-

-400

4.0

Input/Output Enable. Output to enable external hybrid to the

address/data bus.

74

SELECT

(6)

-0.7

-

-

Select. Input from the CPU. When active, selects CT2553 for operation.

75

READYD

-

-

-400

4.0

Ready Data. When active indicates data has been received from, or is

available to, the CPU.

76

TAGEN

-

-

-400

4.0

Tag Enable. Enables an external time to counter for transferring the

time tag word into memory.

77

+5VA

-

-

-

-

+5V input/power supply for channel A transceiver.

78

TX/RX-A

-

-

-

-

Transmit/Receive transceiver-A. Inverted I/O to the coupling

5. Internal Pull-up Resistor = 30K Ohms, typ.

6. Internal Pull-up Resistor = 16K Ohms, typ.

7. Pin 13 = B6, Pin 15 = B7 and Pin 52 = B8 (MSB). B6, B7 and B8 are the MSB lines of an 8 BIT Counter used in the BC and MT

mode to count 32 WORD TRANSFERS to memory (16 words received off the bus) for a total of 128 DATA and Tag words (in

MT mode). (See pages 19 & 20 for discussion.)

Table 7A – CT2553 Pin Function Table (78 Pin DIP) (continued)

Pin

Name

Description