Aeroflex Circuit Technology

29

SCDCT2553 REV B 8/6/99 Plainview NY (516) 694-6700

A02 (38)

A01

A00

MEM/REG

D15-D00

IOEN

SELECT

STRBD

(Internal)

16MHz Clock

RD/WR

READYD

See Note

td1

td8

tpw1

DATA FROM EXTERNAL REGISTER

EXTEN

td2

Figure 32 – CPU Reads from External Register Timing

NOTE: STRBD to IOEN (low) delay is two clock cycles. If contention occurs, delay is two clock cycles following release of bus.

CPU Reads from External Register Timing

SYMBOL

DESCRIPTION

MIN

MAX

UNITS

td1

READYD low delay (CPU Handshake)

-

150

ns

td2

IOEN high delay (CPU Handshake)

-

20

ns

tpw1

READYD pulse width (CPU Handshake)

50

-

ns

td8

Register Data/Address set-up time

-

40

ns

tr

READYD to STRBD release

-

1.37

µs

tz

-

1.8

µs

tz

tr