OR2C04A datasheet(166/192 Pages) ETC

166 / 192 page

Data Sheet

ORCA Series 2 FPGAs

June 1999

166

Lucent Technologies Inc.

Timing Characteristics (continued)

Note: Daisy chaining of FPGAs is not supported in this mode.

Figure 71. Slave Parallel Configuration Mode Timing Diagram

Table 53A. OR2CxxA/OR2TxxA Slave Parallel Configuration Mode Timing Characteristics

OR2CxxA Commercial: VDD = 5.0 V ± 5%, 0 °C

≤ TA ≤ 70 °C; OR2CxxA Industrial: VDD = 5.0 V ± 10%, –40 °C ≤ TA ≤ +85 °C.

OR2TxxA Commercial: VDD = 3.0 V to 3.6 V, 0 °C

≤ TA ≤ 70 °C; OR2TxxA Industrial: VDD = 3.0 V to 3.6 V, –40 °C ≤ TA ≤ +85 °C.

Parameter

Symbol

Min

Max

Unit

CS0

, CS1, WR Setup Time

TS1

—

CS0

, CS1, WR Hold Time

TH1

—

D[7:0] Setup Time

TS2

—

D[7:0] Hold Time

TH2

0—

CCLK High Time

TCH

—

CCLK Low Time

TCL

—

CCLK Frequency

—10

MHz

Table 53B. OR2TxxB Slave Parallel Configuration Mode Timing Characteristics

OR2TxxB Commercial: VDD = 3.0 V to 3.6 V, 0 °C

≤ TA ≤ 70 °C; OR2TxxB Industrial: VDD = 3.0 V to 3.6 V, –40 °C ≤ TA ≤ +85 °C.

Parameter

Symbol

Min

Max

Unit

CS0

, CS1, WR Setup Time

TS1

———

CS0

, CS1, WR Hold Time

TH1

—

D[7:0] Setup Time

TS2

—

D[7:0] Hold Time

TH2

0—

CCLK High Time

TCH

12.5

—

CCLK Low Time

TCL

12.5

—

CCLK Frequency

—40

MHz

5-2848(F)

TS1

TH1

TS2

TH2

CS1

CCLK

D[7:0]

CS0

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