OR2C04A datasheet(164/192 Pages) ETC

164 / 192 page

Data Sheet

ORCA Series 2 FPGAs

June 1999

164

Lucent Technologies Inc.

Timing Characteristics (continued)

Note: Serial data is transmitted out on DOUT 1.5 clock cycles after the byte is input D[7:0].

Figure 69. Synchronous Peripheral Configuration Mode Timing Diagram

Table 51A. OR2CxxA/OR2TxxA Synchronous Peripheral Configuration Mode Timing Characteristics

OR2CxxA Commercial: VDD = 5.0 V ± 5%, 0 °C

≤ TA ≤ 70 °C; OR2CxxA Industrial: VDD = 5.0 V ± 10%, –40 °C ≤ TA ≤ +85 °C.

OR2TxxA Commercial: VDD = 3.0 V to 3.6 V, 0 °C

≤ TA ≤ 70 °C; OR2TxxA Industrial: VDD = 3.0 V to 3.6 V, –40 °C ≤ TA ≤ +85 °C.

Parameter

Symbol

Min

Max

Unit

D[7:0] Setup Time

—

D[7:0] Hold Time

0—

CCLK High Time

TCH

—

CCLK Low Time

TCL

—

CCLK Frequency

—10

MHz

CCLK to DOUT

—30

Table 51B. OR2TxxB Synchronous Peripheral Configuration Mode Timing Characteristics

OR2TxxB Commercial: VDD = 3.0 V to 3.6 V, 0 °C

≤ TA ≤ 70 °C; OR2TxxB Industrial: VDD = 3.0 V to 3.6 V, –40 °C ≤ TA ≤ +85 °C.

Parameter

Symbol

Min

Max

Unit

D[7:0] Setup Time

—

D[7:0] Hold Time

0—

CCLK High Time

TCH

12.5

—

CCLK Low Time

TCL

12.5

—

CCLK Frequency

—40

MHz

CCLK to DOUT

—10

5-4534(F)

CCLK

INIT

D[7:0]

DOUT

RDY

BYTE 0

BYTE 1

TINIT_CLK

TCH

TCL

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