OR2C04A datasheet(163/192 Pages) ETC

163 / 192 page

Data Sheet

June 1999

ORCA Series 2 FPGAs

Lucent Technologies Inc.

163

Timing Characteristics (continued)

* This parameter is valid whether the end of not RDY is determined from the RDY/RCLK pin or from the D7 pin.

Notes:

Serial data is transmitted out on DOUT on the falling edge of CCLK after the byte is input D[7:0].

D[6:0] timing is the same as the write data port of the D7 waveform because D[6:0] are not enabled.

Figure 68. Asynchronous Peripheral Configuration Mode Timing Diagram

Table 50. Series 2 Asynchronous Peripheral Configuration Mode Timing Characteristics

OR2CxxA Commercial: VDD = 5.0 V ± 5%, 0 °C

≤ TA ≤ 70 °C; OR2CxxA Industrial: VDD = 5.0 V ± 10%, –40 °C ≤ TA ≤ +85 °C.

OR2TxxA/B Commercial: VDD = 3.0 V to 3.6 V, 0 °C

≤ TA ≤ 70 °C; OR2TxxA/B Industrial: VDD = 3.0 V to 3.6 V,

–40 °C

≤ TA ≤ +85 °C.

Parameter

Symbol

Min

Max

Unit

, CS0, and CS1 Pulse Width

TWR

100

—

D[7:0] Setup Time

—

D[7:0] Hold Time

0—

RDY Delay

TRDY

—60

RDY Low

CCLK Periods

Earliest WR After RDY Goes High*

TWR2

0—

to D7 Enable/Disable

TDEN

—60

CCLK to DOUT

—30

5-4533.a

CS1

CCLK

DOUT

CS0

RDY

TWR

TRDY

PREVIOUS BYTE

TWR2

WRITE DATA

TDEN

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