OR2C04A datasheet(161/192 Pages) ETC

161 / 192 page

Data Sheet

June 1999

ORCA Series 2 FPGAs

Lucent Technologies Inc.

161

Timing Characteristics (continued)

Note: Serial configuration data is transmitted out on DOUT on the falling edge of CCLK after it is input DIN.

Figure 66. Master Serial Configuration Mode Timing Diagram

Table 48. Series 2 Master Serial Configuration Mode Timing Characteristics

OR2CxxA Commercial: VDD = 5.0 V ± 5%, 0 °C

≤ TA ≤ 70 °C; OR2CxxA Industrial: VDD = 5.0 V ± 10%, –40 °C ≤ TA ≤ +85 °C.

OR2TxxA/B Commercial: VDD = 3.0 V to 3.6 V, 0 °C

≤ TA ≤ 70 °C; OR2TxxA/B Industrial: VDD = 3.0 V to 3.6 V,

–40 °C

≤ TA ≤ +85 °C.

Parameter

Symbol

Min

Nom

Max

Unit

DIN Setup Time

60.0

—

DIN Hold Time

0—

—

CCLK Frequency (M3 = 0)

3.8

10.0

15.2

MHz

CCLK Frequency (M3 = 1)

0.48

1.25

1.9

MHz

CCLK to DOUT Delay

——

5-4532(F)

DIN

CCLK

DOUT

BIT N

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