OR2C04A datasheet(158/192 Pages) ETC

158 / 192 page

Data Sheet

ORCA Series 2 FPGAs

June 1999

158

Lucent Technologies Inc.

Timing Characteristics (continued)

Table 47. Series 2 General Configuration Mode Timing Characteristics

OR2CxxA Commercial: VDD = 5.0 V ± 5%, 0 °C

≤ TA ≤ 70 °C; OR2CxxA Industrial: VDD = 5.0 V ± 10%, –40 °C ≤ TA ≤ +85 °C.

OR2TxxA/B Commercial: VDD = 3.0 V to 3.6 V, 0 °C

≤ TA ≤ 70 °C; OR2TxxA/B Industrial: VDD = 3.0 V to 3.6 V,

–40 °C

≤ TA ≤ +85 °C.

Parameter

Symbol

Min

Max

Unit

All Configuration Modes

M[3:0] Setup Time to INIT High

TSMODE

50.0

—

M[3:0] Hold Time from INIT High

THMODE

600.0

—

RESET

Pulse Width Low to Start Reconfiguration

TRW

50.0

—

PRGM

Pulse Width Low to Start Reconfiguration

TPGW

50.0

—

Master and Asynchronous Peripheral Modes

Power-on Reset Delay

CCLK Period (M3 = 0)

(M3 = 1)

Configuration Latency (noncompressed):

OR2C/2T04A

(M3 = 0)

(M3 = 1)

OR2C/2T06A

(M3 = 0)

(M3 = 1)

OR2C/2T08A

(M3 = 0)

(M3 = 1)

OR2C/2T10A

(M3 = 0)

(M3 = 1)

OR2C/2T12A

(M3 = 0)

(M3 = 1)

OR2C/2T15A/2T15B

(M3 = 0)

(M3 = 1)

OR2C/2T26A

(M3 = 0)

(M3 = 1)

OR2C/2T40A/2T40B

(M3 = 0)

(M3 = 1)

TPO

TCCLK

TCL

17.30

66.0

528.00

4.31

34.48

6.00

48.00

7.62

60.96

9.82

78.56

11.86

94.88

14.57

116.56

20.25

162.00

31.29

250.32

69.47

265.00

2120.00

17.30*

138.40*

24.08*

192.64*

30.60*

244.80*

39.43*

315.44*

47.62*

380.96*

58.51*

468.08*

81.32*

650.56*

125.62*

1004.96*

Slave Serial and Synchronous Peripheral Modes

Power-on Reset Delay

CCLK Period (OR2CxxA/OR2TxxA)

CCLK Period (OR2TxxB)

Configuration Latency (noncompressed):

OR2C/2T04A

OR2C/2T06A

OR2C/2T08A

OR2C/2T10A

OR2C/2T12A

OR2C/2T15A

OR2T15B

OR2C/2T26A

OR2C/2T40A

OR2T40B

TPO

TCCLK

TCL

4.33

100.00

25.00

6.53

9.09

11.55

14.88

17.97

22.08

5.52

30.69

47.40

11.85

17.37

—

* Not applicable to asynchronous peripheral mode.

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