OR2C04A datasheet(162/192 Pages) ETC

162 / 192 page

Data Sheet

ORCA Series 2 FPGAs

June 1999

162

Lucent Technologies Inc.

Timing Characteristics (continued)

Notes:

The RCLK period consists of seven CCLKs for RCLK low and one CCLK for RCLK high.

Serial data is transmitted out on DOUT 1.5 CCLK cycles after the byte is input D[7:0]

f.44(F)

Figure 67. Master Parallel Configuration Mode Timing Diagram

Table 49. Series 2 Master Parallel Configuration Mode Timing Characteristics

OR2CxxA Commercial: VDD = 5.0 V ± 5%, 0 °C

≤ TA ≤ 70 °C; OR2CxxA Industrial: VDD = 5.0 V ± 10%, –40 °C ≤ TA ≤ +85 °C.

OR2TxxA/B Commercial: VDD = 3.0 V to 3.6 V, 0 °C

≤ TA ≤ 70 °C; OR2TxxA/B Industrial: VDD = 3.0 V to 3.6 V,

–40 °C

≤ TA ≤ +85 °C.

Parameter

Symbol

Min

Max

Unit

RCLK to Address Valid

TAV

200

D[7:0] Setup Time to RCLK High

—

D[7:0] Hold Time to RCLK High

0—

RCLK Low Time (M3 = 0)

TCL

462

1855

RCLK High Time (M3 = 0)

TCH

265

RCLK Low Time (M3 = 1)

TCL

3696

14840

RCLK High Time (M3 = 1)

TCH

528

2120

CCLK to DOUT

—30

A[17:0]

RCLK

D[7:0]

TCL

TCH

TAV

CCLK

DOUT

BYTE N

BYTE N + 1

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