OR3LP26B datasheet(152/184 Pages) AGERE

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ORCA OR3LP26B FPSC

Data Sheet

Embedded Master/Target PCI Interface

March 2000

152

Lucent Technologies Inc.

Pin Information (continued)

Table 68. FPGA Common-Function Pin Descriptions (continued)

* The

ORCA Series 3 FPGA data sheet contains more information on how to control these signals during start-up. The timing of DONE release

is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration pins (and the activation of all

user I/Os) is controlled by a second set of options.

Symbol

I/O

Description

Special-Purpose Pins (continued)

TDI, TCK, TMS

If boundary scan is used, these pins are test data in, test clock, and test mode select

inputs. If boundary scan is not selected, all boundary-scan functions are inhibited

once configuration is complete. Even if boundary scan is not used, either TCK or

TMS must be held at logic 1 during configuration. Each pin has a pull-up enabled

during configuration.

I/O

After configuration, these pins are user-programmable I/O.*

RDY/RCLK/

MPI_ALE

ODuring configuration in peripheral mode, RDY/RCLK indicates another byte can be

written to the FPGA. If a read operation is done when the device is selected, the

same status is also available on D7 in asynchronous peripheral mode.

ODuring the Master parallel configuration mode, RCLK is a read output signal to an

external memory. This output is not normally used.

IIn

i960 microprocessor mode, this pin acts as the address latch enable (ALE) input.

I/O

After configuration, if the MPI is not used, this pin is a user-programmable I/O pin.*

HDC

High During Configuration is output high until configuration is complete. It is used as

a control output indicating that configuration is not complete.

LDC

OLow During Configuration is output low until configuration is complete. It is used as a

control output indicating that configuration is not complete.

INIT

I/O

INIT

is a bidirectional signal before and during configuration. During configuration, a

pull-up is enabled, but an external pull-up resistor is recommended. As an active-

low open-drain output, INIT is held low during power stabilization and internal clear-

ing of memory. As an active-low input, INIT holds the FPGA in the wait-state before

the start of configuration.

CS0

, CS1

CS0

and CS1 are used in the asynchronous peripheral, slave parallel, and micropro-

cessor configuration modes. The FPGA is selected when CS0 is low and CS1 is

high. During configuration, a pull-up is enabled.

I/O

After configuration, these pins are user-programmable I/O pins.*

/MPI_STRB

is used in the asynchronous peripheral configuration mode. A low on RD

changes D7 into a status output. As a status indication, a high indicates ready, and a

low indicates busy. WR and RD should not be used simultaneously. If they are, the

write strobe overrides.

This pin is also used as the microprocessor interface (MPI) data transfer strobe. For

PowerPC, it is the transfer start (TS). For i960, it is the address/data strobe (ADS).

I/O

After configuration, if the MPI is not used, this pin is a user-programmable I/O pin.*

is used in the asynchronous peripheral configuration mode. When the FPGA is

selected, a low on the write strobe, WR, loads the data on D[7:0] inputs into an

internal data buffer. WR and RD should not be used simultaneously. If they are, the

write strobe overrides.

I/O

After configuration, this pin is a user-programmable I/O pin.*

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