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OR3LP26B Datasheet(PDF) 156 Page - Agere Systems

Part # OR3LP26B
Description  Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface
PDF  184 Pages
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Manufacturer  AGERE [Agere Systems]
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OR3LP26B Datasheet(HTML) 156 Page - Agere Systems

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ORCA OR3LP26B FPSC
Data Sheet
Embedded Master/Target PCI Interface
March 2000
156
Lucent Technologies Inc.
Lucent Technologies Inc.
Pin Information (continued)
Table 70. Pinout Information (continued)
* These pads are connected to a power plane in the package rather than to a particular pin. The entry's location in the table indicates the posi-
tion of the power pad relative to nearby signal pads.
† Pins marked No Connect must be left unconnected.
‡ These pins are connected to a power plane in the package rather than to a particular pad.
OR3LP26B Pad
Function
PBGA 352
PBGAM 680
PL8C
I/O
J4
M4
PL8B
I/O
H1
M2
PL8A
I/O-A2
H3
M1
PL9D
I/O
J2
N5
PL9C
I/O
J1
N4
PL9B
I/O
K2
N3
PL9A
I/O-A3
J3
N2
VDD
VDD
VDD*VDD*
PL10D
I/O
K1
—
VDD2VDD2—
VDD2
PL10C
I/O
—
N1
PL10B
I/O
—
P5
PL10A
I/O
K4
P4
PL11D
I/O
L2
P3
PL11C
I/O
—
P2
PL11B
I/O
—
P1
PL11A
I/O-A4
K3
R5
VSS
VSS
VSS*VSS*
PL12D
I/O
L1
R4
PL12C
I/O
—
R2
PL12B
I/O
—
R1
PL12A
I/O
M2
—
VDD2VDD2—
VDD2
PL13D
I/O
M1
T5
PL13C
I/O
—
T4
PL13B
I/O
—
T2
PL13A
I/O
L3
T1
VSS
VSS
VSS*VSS*
PECKL
I-ECKL
N2
U5
PL14D
—
—
—
PL14C
I/O
M4
U3
PL14B
I/O
N1
U2
PL14A
I/O-MPI_CLK
M3
U1
VDD
VDD
VDD*VDD*
PL15D
I/O
P2
V1
PL15C
——
—
—
VDD2VDD2P4
VDD2



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