OR3LP26B datasheet(153/184 Pages) AGERE

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Lucent Technologies Inc.

153

Data Sheet

ORCA OR3LP26B FPSC

March 2000

Embedded Master/Target PCI Interface

Lucent Technologies Inc.

Pin Information (continued)

Table 68. FPGA Common-Function Pin Descriptions (continued)

* The

ORCA Series 3 FPGA data sheet contains more information on how to control these signals during start-up. The timing of DONE release

is controlled by one set of bit stream options, and the timing of the simultaneous release of all other configuration pins (and the activation of all

user I/Os) is controlled by a second set of options.

Symbol

I/O

Description

Special-Purpose Pins (continued)

MPI_IRQ

MPI

active-low interrupt request output.

I/O

If the MPI is not in use, this is a user-programmable I/O.

MPI_BI

PowerPC mode MPI burst inhibit output.

I/O

If the MPI is not in use, this is a user-programmable I/O.

MPI_ACK

OIn

PowerPC mode MPI operation, this is the active-high transfer acknowledge (TA)

output. For

i960 MPI operation, it is the active-low ready/record (RDYRCV) output.

If the MPI is not in use, this is a user-programmable I/O.

MPI_RW

PowerPC mode MPI operation, this is the active-low write/ active-high read control

signals. For

i960 operation, it is the active-high write/active-low read control signal.

I/O

If the MPI is not in use, this is a user-programmable I/O.

MPI_CLK

This is the clock used for the synchronous MPI interface. For

PowerPC, it is the CLK-

OUT signal. For

i960, it is the system clock that is chosen for the i960 external bus

interface.

I/O

If the MPI is not in use, this is a user-programmable I/O.

A[4:0]

For

PowerPC operation, these are the PowerPC address inputs. The address bit

mapping (in

PowerPC/FPGA notation) is A[31]/A[0], A[30]/A[1], A[29]/A[2], A[28]/

A[3], A[27]/A[4]. Note that A[27]/A[4] is the MSB of the address. The A[4:2] inputs

are not used in

i960 MPI mode.

I/O

If the MPI is not in use, this is a user-programmable I/O.

A[1:0]/MPI_BE[1:0]

IFor

i960 operation, MPI_BE[1:0] provide the i960 byte enable signals, BE[1:0], that are

used as address bits A[1:0] in

i960 byte-wide operation.

D[7:0]

During Master parallel, peripheral, and slave parallel configuration modes, D[7:0]

receive configuration data, and each pin has a pull-up enabled. During serial config-

uration modes, D0 is the DIN input. D[7:0] are also the data pins for

PowerPC micro-

processor mode and the address/data pins for

i960 microprocessor mode.

I/O

After configuration, the pins are user-programmable I/O pins.*

DIN

During slave serial or Master serial configuration modes, DIN accepts serial configu-

ration data synchronous with CCLK. During parallel configuration modes, DIN is the

D0 input. During configuration, a pull-up is enabled.

I/O

After configuration, this pin is a user-programmable I/O pin.*

DOUT

During configuration, DOUT is the serial data output that can drive the DIN of daisy-

chained slave LCA devices. Data out on DOUT changes on the falling edge of

CCLK.

I/O

After configuration, DOUT is a user-programmable I/O pin.*

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