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OR3LP26B Datasheet(PDF) 165 Page - Agere Systems

Part # OR3LP26B
Description  Field-Programmable System Chip (FPSC) Embedded Master/Target PCI Interface
PDF  184 Pages
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Manufacturer  AGERE [Agere Systems]
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OR3LP26B Datasheet(HTML) 165 Page - Agere Systems

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Lucent Technologies Inc.
165
Data Sheet
ORCA OR3LP26B FPSC
March 2000
Embedded Master/Target PCI Interface
Lucent Technologies Inc.
Pin Information (continued)
Table 70. Pinout Information (continued)
* These pads are connected to a power plane in the package rather than to a particular pin. The entry's location in the table indicates the posi-
tion of the power pad relative to nearby signal pads.
† Pins marked No Connect must be left unconnected.
‡ These pins are connected to a power plane in the package rather than to a particular pad.
OR3LP26B Pad
Function
PBGA 352
PBGAM 680
PR9B
I/O
K23
N33
PR9C
I/O
J25
N32
PR9D
I/O
K24
N31
PR8A
I/O
J26
N30
PR8B
I/O
H25
M34
PR8C
I/O
H26
M33
PR8D
I/O
J24
M31
VSS
VSS
VSS*VSS*
PR7A
I/O-RD
G25
M30
PR7B
I/O
—
L34
PR7C
I/O
—
L33
PR7D
I/O
—
L31
PR6A
I/O
H23
L30
PR6B
I/O
—
K34
PR6C
I/O
G26
K33
PR6D
I/O
—
K32
VDD
VDD
VDD*VDD*
PR5A
I/O
H24
K31
PR5B
I/O
—
K30
PR5C
I/O
—
J34
PR5D
I/O
—
J33
PR4A
—
—
—
VDD2VDD2F25
VDD2
PR4B
I/O
G23
J32
PR4C
I/O
F26
J31
PR4D
I/O
G24
J30
VSS
VSS
VSS*VSS*
PR3A
I/O-WR
E25
H34
PR3B
I/O
E26
H33
PR3C
I/O
—
H31
PR3D
I/O
F24
H30
PR2A
I/O
D25
G34
PR2B
I/O
—
G33
PR2C
I/O
—
G31
PR2D
I/O
E23
G30
VDD
VDD
VDD*VDD*
PR1A
I/O
D26
F34
PR1B
I/O
E24
F32



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