T7630 datasheet(13/210 Pages) AGERE

13 / 210 page

Lucent Technologies Inc.

Preliminary Data Sheet

October 2000

T7630 Dual T1/E1 5.0 V Short-Haul Terminator (Terminator-II)

Lucent Technologies Inc.

Feature Descriptions (continued)

Signaling:

— DS1: extended superframe 2-state, 4-state, and

16-state per-channel robbed bit.

— DS1: D4 superframe 2-state and 4-state per-

channel robbed bit.

— DS1:

SLC-96 superframe 2-state, 4-state, 9-state,

and 16-state per-channel robbed bit.

— DS1: channel-24 message-oriented signaling.

— ITU CEPT: channel associated signaling (CAS).

— Transparent (all data channels).

Alarm reporting, performance monitoring, and main-

tenance:

—

ANSI T1.403-1995, AT&T TR 54016, and ITU

G.826 standard error checking.

— Error and status counters.

— Bipolar violations.

— Errored frame alignment signals.

— Errored CRC checksum block.

— CEPT: received E bit = 0.

— Errored, severely errored, and unavailable sec-

onds.

— Selectable errored event monitoring for errored

and severely errored seconds processing with

programmable thresholds for errored and severely

errored second monitoring.

— CEPT: Selectable automatic transmission of E bit

to the line.

— CEPT: Sa6 coded remote end CRC-4 error E bit =

0 events.

— Programmable automatic and on-demand alarm

transmission.

1. Automatic transmission of remote frame alarm

to the line while in loss of frame alignment

state.

2. Automatic transmission of alarm indication sig-

nal (AIS) to the system while in loss of frame

alignment state.

— Multiple loopback modes.

— Optional automatic line and payload loopback

activate and deactivate modes.

— CEPT nailed-up connect loopback and CEPT

nailed-up broadcast transmission TS-X in TS-0

transmit mode.

— Selectable test patterns for line transmission.

— Detection of framed and unframed pseudorandom

and quasi-random test patterns.

— Programmable squelch and idle codes.

System interface:

— Autonomous transmit and receive system inter-

faces.

— Independent transmit and receive frame synchro-

nization input signals.

— Independent transmit and receive system inter-

face clock.

— 2.048 Mbits/s, 2.048 MHz concentration highway

interface (CHI) default mode.

— Optional 4.096 Mbits/s and 8.192 Mbits/s data

rates.

— Optional 4.096 MHz, 8.192 MHz, and 16.384 MHz

frequency system clock.

— Programmable clock edge for latching frame syn-

chronization signals.

— Programmable clock edge for latching transmit

and receive data.

— Programmable bit and byte offset.

— Programmable CHI master mode for the genera-

tion of the transmit CHI FS from internal logic with

timing derived from the receive line clock signal.

Digital phase comparator for clock generation in the

receive and transmit paths.

Facility Data Link Features

HDLC or transparent mode.

Automatic transmission of the ESF performance

report messages (PRM).

Detection of the ESF PRM.

Detection of the

ANSI ESF FDL bit-oriented codes.

64-byte FIFO in both transmit and receive directions.

Programmable FIFO full- and empty-level interrupt.

SLC-96: FDL transmit and receive register access of

D bits.

User-Programmable Microprocessor Inter-

face

33 MHz read and write access with no wait-states.

12-bit address, 8-bit data interface.

Programmable

Intel or Motorola interface modes.

Demultiplexed or multiplexed address and data bus.

Directly addressable internal registers.

No clock required.

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